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參數(shù)資料
| 型號(hào)： | BN87C51BH |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 12 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁(yè)數(shù)： | 15/16頁(yè) |
| 文件大?。?/td> | 842K |
| 代理商： | BN87C51BH |
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AUTOMOTIVE 80C31BH/80C51BH/87C51
ABSOLUTE MAXIMUM RATINGS
Ambient Temperature Under Bias b40 Cto a125 C
Storage Temperature ....................b65 Cto a150 C
Voltage on EA/V PP Pin to VSS...............0V to a13.0V
Voltage on Any Other Pin to VSS.........b0.5V to a6.5V
IOL per I/O pin..................................................15 mA
Power Dissipation...............................................1.5W
(Based on package heat transfer limitations, not de-
vice power consumption).
Typical Junction Temperature (TJ).................+135°C
(Based upon ambient temperature at a125 C)
Typical Thermal Resistance Junction-to-Ambient
(iJA):
PDIP ........................................................75°C/W
PLCC........................................................46°C/W
NOTICE: This is a production data sheet. The specifi-
cations are subject to change without notice.
WARNING: Stressing the device beyond the ``Absolute
Maximum Ratings'' may cause permanent damage.
These are stress ratings only. Operation beyond the
``Operating Conditions'' is not recommended and ex-
tended exposure beyond the ``Operating Conditions''
may affect device reliability.
DC CHARACTERISTICS
:
(TA eb40 Cto a125 C; VCC e 5V g10% (5V g20% EPROM Only); VSS e 0V)
Symbol
Parameter
Min
Typ(1)
Max
Unit
Test
(87C51/80C51BH)
Conditions
VIL
Input Low Voltage (Except EA)
b
0.5
0.2 VCCb0.25
V
VIL1
Input Low Voltage to EA
0
0.2 VCCb0.45
V
VIH
Input High Voltage (Except XTAL1, RST) 0.2VCCa1.0
VCCa0.5
V
VIH1
Input High Voltage (XTAL1, RST)
0.7 VCCa0.1
VCCa0.5
V
VOL
Output Low Voltage (Ports 1, 2, 3)
0.45(7)
VIOL e 1.6 mA(2)
VOL1
Output Low Voltage (Port 0, ALE, PSEN)
0.45(7)
VIOL e 3.2 mA(2)
VOH
Output High Voltage
2.4
V
IOH eb60 mA
(Ports 1, 2, 3, ALE, PSEN)
0.9 VCC
VIOH eb10 mA
VOH1
Output High Voltage (Port 0 in
2.4
V
IOH eb800 mA
External Bus Mode)
0.9 VCC
VIOH eb80 mA(3)
IIL
Logical 0 Input Current (Ports 1, 2, 3)
b
75
m
AVIN e 0.45 V
ITL
Logical 1-to-0 transition current
b
750
m
A
(4)
(Ports 1, 2, 3)
ILI
Input Leakage Current (Port 0)
g
10
m
AVIN e VIL or VIH
ICC
Power Supply Current:
Active Mode
12 MHz (5)
11.5
25/20
mA
Idle Mode
12 MHz (5)
1.3
6/5
mA
(6)
Power Down Mode
3
100/75
m
AVCC e 2.2V to 5.5V
RRST
Internal Reset Pulldown Resistor
50
300
KX
CIO
Pin Capacitance
10
pF
NOTES
:
1. ``Typicals'' are based on a limited number of samples taken from early manufacturing lots and are not guaranteed. The
values listed are at room temp, 5V.
2. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLs of ALE and Ports
1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1-
to-0 transitions during bus operations. In the worst cases (capacitive loading l 100pF), the noise pulse on the ALE pin may
exceed 0.8V. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt
Trigger STROBE input.
3. Capacitive loading on Ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9 VCC
specification when the address bits are stabilizing.
8
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