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參數(shù)資料
| 型號： | BN80C51FA-1 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 16 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 2/13頁 |
| 文件大小： | 1467K |
| 代理商： | BN80C51FA-1 |
AUTOMOTIVE 80C51FA/83C51FA
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has 5 characters. The first char-
acter is always a `T' (stands for time). The other
characters, depending on their positions, stand for
the name of a signal or the logical status of that
signal. The following is a list of all the characters and
what they stand for.
A: Address
C: Clock
D: Input Data
H: Logic level HIGH
I: Instruction (program memory contents)
L: Logic level LOW, or ALE
P: PSEN
Q: Output Data
R: RD signal
T: Time
V: Valid
W: WR signal
X: No longer a valid logic level
Z: Float
For example,
TAVLL e Time from Address Valid to ALE Low
TLLPL e Time from ALE Low to PSEN Low
AC CHARACTERISTICS
(TA eb40 Cto a125 C, VCC e 5V g10%, VSS e 0V, Load Capacitance
for Port 0, ALE/PROG and PSEN e 100 pF, Load Capacitance for All Other Outputs e 80 pF)
EXTERNAL MEMORY CHARACTERISTICS
Symbol
Parameter
12 MHz Oscillator
Variable Oscillator
Units
Min
Max
Min
Max
1/T CLCL Oscillator Frequency
3.5
16
MHz
TLHLL
ALE Pulse Width
127
2TCLCLb40
ns
TAVLL
Address Valid to ALE Low
43
TCLCLb40
ns
TLLAX
Address Hold After ALE Low
53
TCLCLb30
ns
TLLIV
ALE Low to Valid Instruction In
224
4TCLCLb110
ns
TLLPL
ALE Low to PSEN Low
53
TCLCLb30
ns
TPLPH
PSEN Pulse Width
205
3TCLCLb45
ns
TPLIV
PSEN Low to Valid Instruction In
135
3TCLCLb115
ns
TPXIX
Input Instr Hold After PSEN Trans
0
ns
TPXIZ
Input Instr Float After PSEN Trans
59
TCLCLb25
ns
TAVIV
Address to Valid Instruction In
302
5TCLCLb115
ns
TPLAZ
PSEN Low to Address Float
10
ns
TRLRH
RD Pulse Width
400
6TCLCLb100
ns
TWLWH
WR Pulse Width
400
6TCLCLb100
ns
TRLDV
RD Low to Valid Data In
242
5TCLCLb175
ns
TRHDX
Data Hold After RD High
b
10
b
10
ns
TRHDZ
Data Float After RD High
107
2TCLCLb60
ns
TLLDV
ALE Low to Valid Data In
507
8TCLCLb160
ns
TAVDV
Address Valid to Valid Data In
575
9TCLCLb175
ns
TLLWL
ALE Low to RD or WR Low
200
300
3TCLCLb50
3TCLCLa50
ns
TAVWL
Data Valid to WR Low
203
4TCLCLb130
ns
TQVWX
Address Valid before WR Low
23
TCLCLb50
ns
TWHQX
Data Hold after WR High
33
TCLCLb50
ns
TQVWH
Data Valid to WE High
433
7TCLCLb150
ns
TRLAZ
RD Low to Address Float
0
ns
TWHLH
RD or WR High to ALE High
43
123
TCLCLb40
TCLCLa40
ns
10
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