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參數(shù)資料
| 型號(hào)： | BL34118 |
| 廠商： | 上海貝嶺股份有限公司 |
| 英文描述： | Voice Switched Speakerphone Circuit |
| 中文描述： | 語(yǔ)音開(kāi)關(guān)揚(yáng)聲器電路 |
| 文件頁(yè)數(shù)： | 2/11頁(yè) |
| 文件大?。?/td> | 567K |
| 代理商： | BL34118 |
BL34118
http://www.belling.com.cn
- 2 -
8/15/2006
Total
11 Pages
Wrote by 2006
PIN DESCRPTION
Pin
Name
1
FO
Description
Filter output. Output impedance is less than 50 ohms.
2
FI
Filter input. Input impedance is greater than 1.0 Mohm.
3
CD
Chip Disable. A logic low (<0.8V) sets normal operation. A logic high (>2.0V) disables the IC to
conserve power. Input impedance is nominally 90 k
.
A supply voltage of +2.8 to +6.5 volts is required, at
≈
5.0 mA. As Vcc falls from 3.5 to 2.8 volts, an
AGC circuit reduces the receive attenuator gain by
≈
25 db (when in the receive mode).
Output of the second hybrid amplifier. The gain is internally set at –1.0 to provide a differential
4
VCC
5
HTO+
output, in conjunction with HTO-, to the hybrid transformer.
6
HTO-
Output of the first hybrid amplifier. The gain of the amp is set by external resistors.
Input and summing node for the first hybrid amplifier. DC level is
≈
VB.
Output of the transmit attenuator. DC level is approximately VB.
Input to the transmit attenuator. Max. signal level is 350 mVrms. Input impedance is
≈
10 k
.
Output of the microphone amplifier. The gain of the amplifier is set by external resistors.
Input and summing node of the microphone amplifier. DC level is
≈
VB.
Mute input. A logic low (<0.8V) sets normal operation. A logic high (>2.0V) mutes the microphone
7
HTI
8
TXO
9
TXI
10
MCO
11
MCI
12
MUT
amplifier without affecting the rest of the circuit. Input impedance is nominally 90 k
.
13
VLC
Volume control input. When VLC = VB, the receive attenuator is at maximum gain when in the
receive mode. When VLC = 0.3VB, the receive gain is down 35 dB. Does not affect the transmit
mode.
14
CT
An RC at this pin sets the response time for the circuit to switch modes.
An output voltage
≈
Vcc/2. This voltage is a system as ground, and biases the volume control. A
filter cap is required.
15
VB
16
CPT
An RC at this pin sets the time constant for the transmit background monitor.
17
TLI2
Input to the transmit level detector on the mike/speaker side.
18
TLO2
Output of the transmit level detector on the mike/speaker side, and input to the transmit
background monitor.
19
RLO2
Output of the receive level detector on the mike/speaker side.
20
RLI2
Input to the receive level detector on the mike/speaker side.
21
RXI
Input to the receive attenuator and dial tone detector. Max input level is 350 mVrms. Input
impedance is
≈
10 k
.
Output of the receive attenuator. DC level is approximately VB.
22
RXO
23
TLI1
Input to the transmit level detector on the line side.
24
TLO1
Output of the transmit level detector on the line side.
25
RLO1
Output of the receive level detector on the line side, and input to the receive background monitor.
26
RLI1
Input to the receive level detector on the line side.
27
CPR
An RC at this pin sets the time constant for the receive background monitor.
28
GND
Ground pin for the entire IC.
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