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參數(shù)資料
| 型號： | BH7673G-TR |
| 廠商： | Rohm Semiconductor |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC VIDEO ISOLATION AMP SSOP5 |
| 標準包裝： | 3,000 |
| 應(yīng)用： | 通用 |
| 電路數(shù)： | 1 |
| 電流 - 電源： | 4.8mA |
| 電壓 - 電源，單路/雙路(±)： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 6-TFSOP（0.063"，1.60mm 寬），5 引線 |
| 供應(yīng)商設(shè)備封裝： | 5-SSOP |
| 包裝： | 帶卷 (TR) |
IDT / ICS 700MHZ, 3.3V LVPECL FREQUENCY SYNTHESIZER
10
ICS8430B-71 REV A NOVEMBER 20, 2006
ICS8430B-71
700MHZ, CRYSTAL INTERFACE/LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
V
CC - 2V
50
50
RTT
Z
o = 50
Z
o = 50
FOUT
FIN
RTT =
Z
o
1
((V
OH + VOL) / (VCC – 2)) – 2
3.3V
125
125
84
84
Z
o = 50
Z
o = 50
FOUT
FIN
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, termi-
nating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
drive 50
transmission lines. Matched impedance techniques
FIGURE 4B. LVPECL OUTPUT TERMINATION
FIGURE 4A. LVPECL OUTPUT TERMINATION
should be used to maximize operating frequency and minimize
signal distortion. There are a few simple termination schemes.
Figures 4A and 4B show two different layouts which are rec-
ommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and
clock component process variations.
TERMINATION FOR LVPECL OUTPUTS
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