
Ultra Low Power/High Speed CMOS SRAM
2M X 8 bit
BH62UV1600
BSI
R0201-BH62UV1600
Revision 1.0
Jul. 2005
1
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FEATURES
Wide V
CC
low operation voltage : 1.65V ~ 3.6V
Ultra low power consumption :
V
CC
= 3.0V
Operation current : 5.0mA at 70ns at 25
O
C
Standby current : 3uA at 25
O
C
V
CC
= 2.0V
Data retention current : 3uA at 25
O
C
High speed access time :
-70
70ns at 1.8V at 85
O
C
Automatic power down when chip is deselected
Easy expansion with CE1, CE2 and OE options
Three state outputs and TTL compatible
Fully static operation, no clock, no refreash
Data retention supply voltage as low as 1.0V
1.5mA at 1MHz at 25
O
C
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DESCRIPTION
The BH62UV1600 is a high performance, ultra low power CMOS Static
Random Access Memory organized as 2,048K by 8 bits and operates in
a wide range of 1.65V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with typical operating current of 1.5mA at
1MHz at 3.6V/25
O
C and maximum access time of 70ns at 1.8V/85
O
C.
Easy memory expansion is provided by an active LOW chip enable
(CE1), an active HIGH chip enable (CE2) and active LOW output
enable (OE) and three-state output drivers.
The BH62UV1600 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BH62UV1600 is made with two chips of 8Mbit SRAM by stacked
multi-chip-package.
The BH62UV1600 is available 48-ball BGA package.
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PRODUCT FAMILY
POWER CONSUMPTION
STANDBY
(I
CCSB1
, Max)
SPEED
(ns)
Operating
(I
CC
, Max)
PRODUCT
FAMILY
OPERATING
TEMPERATURE
V
CC
RANGE
V
CC
=1.8~3.6V
V
CC
=3.6V V
CC
=1.8V V
CC
=3.6V V
CC
=1.8V
PKG TYPE
+0
O
C to +70
O
C
70
20uA
15uA
10mA
7mA
BH62UV1600AI
-25
O
C to +85
O
C
1.65V ~ 3.6V
70
25uA
20uA
10mA
7mA
BGA-48-0608
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PIN CONFIGURATIONS
Brilliance Semiconductor, Inc.
reserves the right to modify document contents without notice.
Detailed product characteristic test report is available upon request and being accepted.
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BLOCK DIAGRAM
G
H
F
E
D
C
B
A
1
2
3
4
5
6
A9
A11
A10
A19
A12
A14
A13
A15
WE
NC
NC
NC
DQ7
A17
A16
A7
VSS
VCC
DQ2
DQ1
DQ6
DQ5
VSS
A5
OE
A3
A0
A6
A4
A1
A2
CE2
NC
NC
NC
CE1
D04
NC
48-ball BGA top view
NC
NC
DQ0
VSS
VCC
D3
NC
A18
A20
A8
Address
Input
Buffer
Row
Decoder
Memory Array
1024 x 16384
Column I/O
Write Driver
Sense Amp
Column Decoder
Address Input Buffer
A15
A13 A16 A2 A1
Data
Input
Buffer
Control
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
8
8
8
8
11
2048
16384
1024
10
A17
A19
Data
Output
Buffer
A14
CE1
CE2
WE
OE
V
CC
GND
A0
A20
A18