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參數(shù)資料
| 型號： | BH3874AKS2 |
| 廠商： | Rohm CO.,LTD. |
| 英文描述： | SPDT SUBMINIATURE POWER RELAY |
| 中文描述： | 聲音處理器IC |
| 文件頁數(shù)： | 13/25頁 |
| 文件大?。?/td> | 261K |
| 代理商： | BH3874AKS2 |
BH3874AKS2
Audio ICs
!
Circuit operations
Timing of Control Signal
90%
90%
90%
10%
10%
10%
tw
tsu
th
ts
tw(LATCH)
tw(DATA)
tw
SCK
(CLOCK signal)
35pin
34pin
SI
DATA signal
LATCH signal
Fig.2
DATA (SI) is read at a rising edge of CLOCK.
DATA is fixed by the rising edge of LATCH.
Be sure to set SCK and SI to Low after latching.
When the CLOCK signal is High, it doesn’t accept LATCH signal.
Constant of Timing Chart (Ta=25
°
C)
Parameter
Hold time (CLOCK
→
CLOCK)
"High" Input voltage
"Low" Input voltage
Clock width
"Middle" Input voltage
Setup time (DATA, CLOCK
→
LATCH)
Serial signal SI is judging DATA and LATCH in the difference of the voltage level.
In the application schematic, it is changing 0-5V 3 line serial data into the 2 line serial data at the voltage with the resistance and
the diode of the external.
We request enough examination, because there is a case where the voltage which is changed by the ability for the microcomputer to
drive and the external parts.
Data width
Latch width
Setup time (DATA
→
CLOCK)
Symbol
V
IH
V
IM
V
IL
tw
tw (DATA)
tw (LATCH)
tsu
th
ts
3.3
1.8
0.3
2.0
4.0
2.0
1.0
1.0
1.0
2.0
0
2.4
1.2
5.0
6.0
V
V
μ
s
V
μ
s
μ
s
μ
s
μ
s
μ
s
Min.
Typ.
Max.
Unit
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