- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1990 > BH2226FV-FE2 (Rohm Semiconductor)IC DAC 8BIT 8-CHAN SSOP-B16 PDF資料下載
參數(shù)資料
| 型號： | BH2226FV-FE2 |
| 廠商： | Rohm Semiconductor |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 8BIT 8-CHAN SSOP-B16 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時(shí)間： | 100µs |
| 位數(shù)： | 8 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 8 |
| 電壓電源： | 單電源 |
| 工作溫度： | -20°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SSOPB |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 輸出數(shù)目和類型： | 8 電壓，單極 |
| 采樣率（每秒）： | * |
| 產(chǎn)品目錄頁面： | 1375 (CN2011-ZH PDF) |
| 其它名稱： | BH2226FV-FE2DKR |
BH2226FV,BH2226F
Technical Note
6/9
www.rohm.com
2009.07 - Rev.B
2009 ROHM Co., Ltd. All rights reserved.
·Command Transmission Procedures
Carry out the following after power on and just after external reset:
(1)
Power Down Release (2) I/O D/A Select (3) I/O Status Set
Note: When power is started, the power on reset is activated and the internal register initialized.
However, as shown in the
figure above, in area (a), if CSB cannot be made High and noise is introduced in the control line an error may occur when
setting during the rising CSB signal.
In such a case, set the external RESETB terminal to Low and reset when CSB = High.
·Parallel - Serial Conversion
Parallel data {DA[8:1]} is taken in at the first CSB falling edge after setting the parallel serial command.
The data is then outputted in synch with the falling edge of the CLK in the next CSB = Low area, and output from 4CLK.
However, please note that the SCLK falling edge that occurs from CSB fall to the first SCLK rising edge is not counted.
·Serial - Parallel Conversion
DI serial data is taken in at the rising edge of the CLK.
The data is then output from the DA[8:1] terminal just after the CSB rising edge.
During that time the SO terminal output becomes undetermined (just previous address setting + data output).
·D/A Converter Output Setting (Fig. 7)
DI serial data is taken in at the rising edge of the clock.
The D/A converter output is output from the DA[8:1] terminal just after the rising edge of the CSB.
During that time, the SO terminal output becomes undetermined (just previous address setting + data output).
Fig.7
Fig.6
Fig.5
Fig.8
Power down release
I/O DAC select
I/O status setting
Arbitrary setting
Parallel data taking in
PS conversion command
Parallel data output
DAC output
DA1 output
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| BH2228FV-E2 | IC DAC 8BIT 6-CHAN SSOP-B14 |
| BQ4285EP | IC RTC W/114X8 NVSRAM 24-DIP |
| BQ4847YMT | IC RTC W/NVSRAM CONTROL T-MOD |
| BU2280FV-E2 | IC CLOCK GEN DVD-VIDEO SSOP-B24 |
| BU2363FV-E2 | IC CLOCK GEN DVD-VIDEO SSOP-B16 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BH2226FV-F-E2 | 制造商:ROHM Semiconductor 功能描述: |
| BH2226GV-E2 | 制造商:ROHM Semiconductor 功能描述: |
| BH2227FV | 制造商:ROHM 制造商全稱:Rohm 功能描述:Standard 8bit 4ch-E6ch Type D/A Converters |
| BH2227FV_09 | 制造商:ROHM 制造商全稱:Rohm 功能描述:Standard 8bit 4ch-E6ch Type D/A Converters |
| BH2227FV_11 | 制造商:ROHM 制造商全稱:Rohm 功能描述:Standard 8bit 4ch?6ch Type D/A Converters |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。