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參數(shù)資料
| 型號： | B9947CA |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 3.3V, 160-MHz, 1:9 Clock Distribution Buffer |
| 中文描述： | 9947 SERIES, LOW SKEW CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | TQFP-32 |
| 文件頁數(shù)： | 3/5頁 |
| 文件大?。?/td> | 57K |
| 代理商： | B9947CA |
B9947
Document #: 38-07078 Rev. *C
Page 3 of 5
Maximum Ratings[2]
Maximum Input Voltage Relative to V
SS
:............ V
SS
–
0.3V
Maximum Input Voltage Relative to V
DD
:.............V
DD
+ 0.3V
Storage Temperature: ................................
–
65
°
C to + 150
°
C
Operating Temperature:................................
–
40
°
C to +85
°
C
Maximum ESD protection.............................................. 2 KV
Maximum Power Supply: ................................................5.5V
Maximum Input Current:
..................................................±
20 mA
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any volt-
age higher than the maximum rated voltages to this circuit. For
proper operation, V
in
and V
out
should be constrained to the
range:
V
SS
< (V
in
or V
out
) < V
DD
Unused inputs must always be tied to an appropriate logic volt-
age level (either V
SS
or V
DD
).
Notes:
2.
3.
4.
5.
6.
7.
8.
9.
10. Part to Part Skew at a given temperature and voltage
The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
Inputs have pull-up resistors that effect input current.
Driving series or parallel terminated 50
(or 50
to V
/2) transmission lines.
Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs.
Outputs driving 50
transmission lines.
50% input duty cycle.
Set-up and Hold times are relative to the falling edge of the input clock
DC Parameters:
V
DDC
= 3.3V ±10%, V
DD
= 3.3V ±10%, T
A
=
–
40
°
C to +85
°
C
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
Input Low Voltage
V
SS
2.0
0.8
V
Input High Voltage
V
DD
–
100
V
I
IL
I
IH
V
OL
V
OH
I
DD
C
in
Input Low Current (@V
IL
= V
SS
)
Input High Current (@V
IL
=V
DD
)
Output Low Voltage
Note 3
μA
10
μA
I
OL
= 20 mA, Note 4
I
OH
=
–
20 mA, V
DDC
= 3.3V, Note 4
All V
DDC
and V
DD
0.4
V
Output High Voltage
2.5
V
Quiescent Supply Current
1
2
mA
Input Capacitance
4
pF
AC Parameters
[5]
:
V
DDC
= 3.3V ±10%, V
DD
= 3.3V ±10%, T
A
=
–
40
°
C to +85
°
C
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
Fmax
Maximum Input Frequency
[6]
TCLK to Q Delay
[6]
Output Duty Cycle
[6,7]
160
MHz
Tpd
4.75
9.25
ns
FoutDC
Measured at V
DDC
/2 TCYCLE/2
–
800
TCYCLE/2 + 800
ps
tpZL, tpZH
Output Enable Time (all outputs)
2
10
ns
tpLZ, tpHZ
Output Disable Time (all outputs)
Output-to-Output Skew
[6,9]
Part to Part Skew
[10]
Set-up Time
[6,8]
Hold Time
[6,8]
Output Clocks Rise/Fall Time
[9]
2
10
ns
Tskew
350
ps
Tskew (pp)
2.0
ns
Ts
SYNC_OE to TCLK
0.0
ps
Th
TCLK to SYNC_OE
1.0
ps
Tr/Tf
0.8V to 2.0V
0.20
1.0
ns
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