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參數(shù)資料
| 型號： | B9947 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 3.3V, 160-MHz, 1:9 Clock Distribution Buffer |
| 中文描述： | 3.3伏，160兆赫，1:9時鐘分配緩沖區(qū) |
| 文件頁數(shù)： | 2/5頁 |
| 文件大小： | 57K |
| 代理商： | B9947 |
B9947
Document #: 38-07078 Rev. *C
Page 2 of 5
Note:
1.
PU = Internal Pull-Up.
Output Enable/Disable
The B9947 features a control input to enable or disable the
outputs. This data is latched on the falling edge of the input
clock. When SYNC_OE is asserted LOW, the outputs are dis-
abled in a LOW state. When SYNC_OE is set HIGH, the out-
puts are enabled as shown in
Figure 1
.
Figure 1. SYNC_OE Timing Diagram
Pin Description
Pin
Name
PWR
I/O
Description
3
TCLK0
I, PU
Test Clock Input
4
TCLK1
I, PU
Test Clock Input
2
TCLK_SEL
I, PU
Test Clock Select Input. When LOW, TCLK0 is selected. When
asserted HIGH, TCLK1 is selected.
11, 13, 15, 19, 21,
23, 26, 28, 30
Q(8:0)
VDDC
O
Clock Outputs
5
SYNC_OE
I, PU
Output Enable Input. When asserted HIGH, the outputs are
enabled and when set LOW the outputs are disabled in a LOW
state.
6
TS#
I, PU
Three-state Control Input. When asserted LOW, the output
buffers are three-stated. When set HIGH, the output buffers
are enabled.
10, 14, 18, 22, 27,
31
VDDC
3.3V Power Supply for Output Clock Buffers
7
VDD
3.3V Power Supply
1, 8, 9, 12, 16, 17,
20, 24, 25, 29, 32
VSS
Common Ground
TCLK
SYNC_OE
Q
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| B9947CA | 制造商: 功能描述: 制造商:undefined 功能描述: |
| B9948 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:3.3V, 160-MHz, 1:12 Clock Distribution Buffer |
| B9948CA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TWELVE DISTRIBUTED-OUTPUT CLOCK DRIVER|TQFP|32PIN|PLASTIC |
| B9948L | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2.5V/3.3V, 160-MHz, 1:12 Clock Distribution Buffer |
| B9948LAA | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:2.5V/3.3V, 160-MHz, 1:12 Clock Distribution Buffer |
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