參數(shù)資料
型號(hào): B300D44A102XXG
廠商: ON Semiconductor
文件頁數(shù): 13/15頁
文件大小: 0K
描述: IC PROCESSOR AUDIO 24BIT 44DFN
標(biāo)準(zhǔn)包裝: 1
系列: BelaSigna® 300
類型: 音頻處理器
應(yīng)用: 便攜式設(shè)備
安裝類型: 表面貼裝
封裝/外殼: 44-VFDFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 44-DFN
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: B300D44A102XXGOSDKR
BelaSigna 300
http://onsemi.com
7
WLCSP Pin Out
A total of 35 active pins are present on the BelaSigna 300 WLCSP package. They are organized in a staggered array. A
description of these pins is given in Table 7.
Table 7. WLCSP PAD DESCRIPTIONS
Pad Index
BelaSigna 300 Pad Name
Description
I/O
A/D
A1
GNDRCVR
Ground for output driver
N/A
A
A5
VBATRCVR
Power supply for output stage
I
A
B2
RCVR_HP+
Extra output driver pad for high power mode
O
A
C3
RCVR+
Output from output driver
O
A
A3
RCVR
Output from output driver
O
A
B4
RCVR_HP
Extra output driver pad for high power mode
O
A
B6
CAP0
Charge pump capacitor pin 0
N/A
A
C5
CAP1
Charge pump capacitor pin 1
N/A
A
A7
VDBL
Doubled voltage
O
A
B8
VBAT
Power supply
I
A
B10
VREG
Regulated supply voltage
O
A
A9
AGND
Analog ground
N/A
A
A11
AI4
Audio signal input 4
I
A
B12
AI2/LOUT2
Audio signal input 2/output signal from preamp 2
I/O
A
A13
AI1/LOUT1
Audio signal input 1/output signal from preamp 1
I/O
A
B14
AI0/LOUT0
Audio signal input 0/output signal from preamp 0
I/O
A
D14
GPIO[4]/LSAD[4]
Generalpurpose I/O 4/low speed AD input 4
I/O
A/D
E13
GPIO[3]/LSAD[3]
Generalpurpose I/O 3/low speed AD input 3
I/O
A/D
C13
GPIO[2]/LSAD[2]
Generalpurpose I/O 2/low speed AD input 2
I/O
A/D
D12
GPIO[1]/LSAD[1]/UARTRX
Generalpurpose I/O 1/low speed AD input 1/and UART RX
I/O
A/D
E11
GPIO[0]/UARTTX
Generalpurpose I/O 0/UART TX
I/O
A/D
C9
GNDC
Digital ground
N/A
A
C11
SDA (I2C)
I2C data
I/O
D
D10
SCL (I2C)
I2C clock
I/O
D
E9
EXT_CLK
External clock input/internal clock output
I/O
D
D8
VDDC
Core logic power
O
A
E7
SPI_CLK
Serial peripheral interface clock
O
D
C7
SPI_SERI
Serial peripheral interface input
I
D
D6
SPI_CS
Serial peripheral interface chip select
O
D
E5
SPI_SERO
Serial peripheral interface output
O
D
D4
PCM_FR
PCM interface frame
I/O
D
E3
PCM_SERI
PCM interface input
I
D
D2
PCM_SERO
PCM interface output
O
D
C1
PCM_CLK
PCM interface clock
I/O
D
E1
Reserved
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