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參數(shù)資料
| 型號： | B250B57A106E1G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 16/30頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP AUDIO 16BIT 57CABGA |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | BelaSigna® 250 |
| 類型： | 音頻處理器 |
| 應(yīng)用： | 便攜式設(shè)備 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 57-VFBGA |
| 供應(yīng)商設(shè)備封裝： | 57-CABGA（5x5） |
| 包裝： | 帶卷 (TR) |
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BELASIGNA 250
http://onsemi.com
23
information on default values associated with each control
register.)
BELASIGNA 250 boots in a twostage boot sequence.
The program ROM begins loading the bootloader from an
external EEPROM 200 ms after power is applied to the chip.
In this process the program ROM checks the bootloader for
validity, which in turn ensures the file system validity. If the
file structure is validated, the bootloader is written to
PRAM. In case of an error while reading the external
EEPROM, all outputs are muted. The system restarts
approximately every second and attempts to reboot.
Once the bootloader is loaded into PRAM the program
counter is set to point to the beginning of the bootloader
code. Subsequently, the signalprocessing application that
is stored in the EEPROM is downloaded to PRAM by the
bootloader. The boot process generally takes less than one
second. ON Semiconductor provides a standard fullfeature
bootloader. A graphical representation of this booting
sequence can be seen in Figure 9.
Figure 9. Booting Sequence
Boot ROM
Program Memory
EEPROM
SDA
MDA
FAT
Bootloader
Application
Boot ROM
Program Memory
EEPROM
SDA
MDA
FAT
Bootloader
Application
Bootloader
Stage 1:
Boot ROM loads Bootloader
from EEPROM to Program
Memory
Stage 2:
Bootloader loads Application from
EEPROM to Program Memory, X
Memory, and Y Memory
Boot ROM
Program Memory
EEPROM
SDA
MDA
FAT
Bootloader
Application
Bootloader
Stage 3:
Application loaded and running
Application
Time
Power Management Strategy
BELASIGNA 250 has a builtin power management unit
that guarantees valid system operation under any voltage
supply condition to prevent any unexpected audio output as
the result of any supply irregularity. The unit constantly
monitors the power supply and shuts down all functional
units (including all units in the audio path) when the power
supply voltage goes below a level at which point valid
operation can no longer be guaranteed.
The power supply operation can be seen in Figure 10.
Once the supply voltage rises above the startup voltage of
the internal regulator that supplies the digital subsystems
(VDDCSTARTUP) and remains there for the length of time
TPOR, a POR will occur. If the supply is consistent, the
internal system voltage will then remain at a fixed nominal
voltage (VDDCNOMINAL). If a spike occurs that causes the
voltage to drop below the shutdown internal system voltage
(VDDCSHUTDOWN), the system will shut down. If the
voltage rises again above the startup voltage and remains
there for the length of time TPOR, a POR will occur. If
operating directly off a battery, the system will not power
down until the voltage drops below the VDDCSHUTDOWN
voltage as the battery dies. This prevents unwanted resets
when the voltage is just on the edge of being too low for the
system to operate properly because the difference between
VDDCSTARTUP and VDDCSHUTDOWN prevents oscillation
around the VDDCSHUTDOWN point.
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