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參數(shù)資料
| 型號： | AZ12010XP |
| 廠商： | Arizona Microtek, Inc. |
| 英文描述： | Multiply by 16, 32 Phase-Locked Loop Clock Generator |
| 中文描述： | 乘以16，32鎖相環(huán)時鐘發(fā)生器 |
| 文件頁數(shù)： | 6/9頁 |
| 文件大?。?/td> | 266K |
| 代理商： | AZ12010XP |
AZ12010
November 2006 * REV - 5
www.azmicrotek.com
6
Loop Filter Design
The combination of the phase detector, amplifier, VCO and divider form a second-order phase-locked loop. Proper
selection of the loop components is important to obtain stable, low jitter operation.
The loop bandwidth (or natural frequency,
ω
n
) and damping factor (
ζ
) are the two major driving forces that define the
loop’s response to a disturbance. The value of
ζ
is typically 0.7 to ensure the fastest step response consistent with no
ringing. However in many oscillator application
ζ
may be 3 or higher to provide further phase noise reduction.
ω
n
is
chosen as a compromise between settling time, VCO jitter and reference feedthrough. These values can be computed by
the following equations:
1
τ
N
ω
τ
ζ =
1
ω
φ
VCO
n
K
K
=
2
2
n
τ
τ
K
K
N
The component definitions are shown in the figure below. R3 should be equal to R1 to minimize integrator offsets.
1
1
1
C
R
=
1
2
2
C
R
=
=
φ
Phase Detector Gain (20.3 radians/V)
=
VCO
VCO Gain (radians/sec/volt)
=
Frequency Divisor value (32)
CHARGE
PUMP
INTREF
INTSUM
INTOUT
CPREF CPOUT
INTEGRATOR
R2
C1
R1
R3
EXTERNAL
VCSO
CONTROL
VOLTAGE
Figure 1 Charge Pump and Integrator
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