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參數(shù)資料
| 型號： | AZ12010BL |
| 廠商： | MINI-CIRCUITS |
| 英文描述： | Multiply by 16, 32 Phase-Locked Loop Clock Generator |
| 中文描述： | 乘以16，32鎖相環(huán)時(shí)鐘發(fā)生器 |
| 文件頁數(shù)： | 4/9頁 |
| 文件大?。?/td> | 266K |
| 代理商： | AZ12010BL |
AZ12010
November 2006 * REV - 5
www.azmicrotek.com
4
AZ12010 FUNCTIONAL PIN/PAD DESCRIPTIONS
Functional Description
Reference Frequency Input
This pin/pad includes an on-chip 470
Ω
pull
down resistor to V
BB
. The input from the reference circuit should be AC
coupled.
Reference Frequency Output
This pin is an inverted and amplified version of
the signal on the REFIN pin. The gain from REFIN to ˉˉˉˉˉˉˉˉ is
approximately 20. If V
EEP
is connected to V
EE
, a 4 ma on-chip current source is
provided for the output.
REFOUT
ˉˉˉˉˉˉˉˉ is not available on the packaged versions (AZ12010A, AZ12010B).
Charge Pump Reference Output
The pin/pad voltage is nominally 1.2 volts
below V
CC
.
Charge Pump Output
The charge pump output voltage is V
CPREF
±
0.3V
during a phase correction pulse. When there is no correction pulse the output
goes high impedance.
Charge Pump Polarity
When this pin/pad is pulled high the PLL operates
with a VCSO circuit exhibiting negative pulling slope (the VCSO frequency
goes down when the control voltage goes up). When this pin/pad is pulled low
(AZM12010B) the PLL operates with a VCSO circuit exhibiting positive
pulling slope (the VCSO frequency goes up when the control voltage goes up).
Name
Logic Level
REFIN
REFOUT
ˉˉˉˉˉˉˉˉ
PECL
CPREF
CPOUT
CPPOL
If the pin/pad is left open (AZM12010A), an internal pullup resistor selects
negative pulling slope mode.
Integrator Reference Input
This pin/pad should be connected to CPREF
through a bias current cancellation network
Integrator Summing Junction
This pin/pad is the summing junction for the
integrator amplifier
Integrator Output
SAW Amplifier Inputs
If only one input is used (Single-ended VCSO), the
unused input should be bypassed with a capacitor to V
BB
.
SAW Amplifier Outputs
These are open collector outputs for driving the
VCSO device. Operating at nominally 9 ma, external pullup resistors must be
connected between these pins/pads and V
CC
. If only one output is used, the
other output should be connected to V
CC
through a 50
resistor.
PLL Output Enable
The Q and Q outputs are enabled when this pin/pad is
pulled high. When this pin/pad is low, the Q output is high, and the Q output is
low. If the pin/pad is left open, an internal pullup resistor enables the outputs.
Divide Select
When this pin/pad is high, the Q and Q outputs are divided by
one from the SAW device. When it is low, the Q and Q outputs are divided by
two from the SAW device. If the pin/pad is left open, an internal pullup resistor
selects the divide by one mode.
Clock Output
These pin/pads are the main clock output. When ENABLE is
low, the outputs are disabled with Q high and Q low.
Reference Voltage Output
This pin/pad is used to bias the REFIN signal. It
must be bypassed externally to the V
EE
pins/pads with a 0.01
μ
F capacitor.
ˉˉˉˉˉˉˉˉ Current Source
If V
EEP
is connected to V
EE
, a 4 ma on-chip current
source is provided for the ˉˉˉˉˉˉˉˉ
output.
V
EEP
is not available on the packaged versions (AZ12010A, AZ12010B).
Positive Supply
+3.0 to +3.6 V
Negative Supply
Ground
LVCMOS
LVTTL
INTREF
INTSUM
INTOUT
SAWIN
SAWIN
ˉˉˉˉˉˉˉ
SAWOUT
ˉˉˉˉˉˉˉˉ
CML (Analog)
ENABLE
LVCMOS
LVTTL
DIV_SEL
LVCMOS
LVTTL
Q
Q
PECL
V
BB
V
EEP
V
CC
V
EE
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