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| 型號： | AZ10LVEL16VSD |
| 廠商： | Arizona Microtek, Inc. |
| 英文描述： | ECL/PECL Differential Receiver with Variable Output Swing |
| 中文描述： | ECL / PECL的差分接收器輸出變秋千 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大小： | 109K |
| 代理商： | AZ10LVEL16VSD |
AZ10LVEL16VS
AZ100LVEL16VS
ECL/PECL Differential Receiver with Variable Output Swing
1630 S. STAPLEY DR., SUITE 127
MESA, ARIZONA 85204
USA
(480) 962-5881
FAX (480) 890-2541
www.azmicrotek.com
ARIZONA MICROTEK, INC.
FEATURES
250ps Propagation Delay
High Bandwidth Output Transitions
Operating Range of 3.0V to 5.5V
Internal Input Pulldown Resistors
Functionally Equivalent to ON
Semiconductor MC10EL16,
MC100EL16 & MC100LVEL16
Variable Output Swing
DESCRIPTION
The
AZ10/100LVEL16VS
differential receiver with variable output swing. The LVEL16VS has functionality and output transition times
similar to the EL16, with an input that controls the amplitude of the Q/Q outputs.
The operational range of the LVEL16VS control input, V
CTRL
, is from V
BB
(full swing) to V
CC
(min. swing).
Maximum swing is achieved by leaving the V
CTRL
pin open or by tying it to the negative supply (V
EE
). Simple
control of the output swing can be obtained by a variable resistor between the V
BB
and V
CC
pins, with the wiper
driving V
CTRL
. Typical application circuits and results are described in this Data Sheet.
The LVEL16VS provides a V
BB
output for single-ended use or a DC bias reference for AC coupling to the
device. For single-ended input applications, the V
BB
reference should be connected to one side of the D/D
differential input pair. The input signal is then fed to the other D/D input. The V
BB
pin can support 1.5mA
sink/source current. When used, the V
BB
pin should be bypassed to ground via a 0.01
μ
F capacitor.
Under open input conditions internal input clamps will force the Q output LOW.
NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.
PIN DESCRIPTION
PIN
FUNCTION
D, D
Data Inputs
V
CTRL
Output Swing Control
Q, Q
Data Outputs
V
BB
Reference Voltage Output
V
CC
Positive Supply
V
EE
Negative Supply
is
a
8
5
6
7
4
3
2
1
VCC
D
VEE
Q
Q
VBB
D
VCTRL
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
PACKAGE AVAILABILITY
PART NUMBER
PACKAGE
MARKING
AZM10
LV16VS
AZM100
LV16VS
AZT
L16VS
AZH
L16VS
NOTES
SOIC 8
AZ10LVEL16VSD
1,2
SOIC 8
AZ100LVEL16VSD
1,2
TSSOP 8
AZ10LVEL16VST
1,2
TSSOP 8
AZ100LVEL16VST
1,2
1
Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts)
Tape & Reel.
Date code format: “Y” or “YY” for year followed by “WW” for week on
underside of part.
2
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