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參數(shù)資料
| 型號： | AZ10ELT22 |
| 廠商： | Arizona Microtek, Inc. |
| 英文描述： | CMOS/TTL to Differential PECL Translator |
| 中文描述： | 的CMOS / TTL到差分PECL翻譯 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大?。?/td> | 81K |
| 代理商： | AZ10ELT22 |
AZ10ELT22
AZ100ELT22
CMOS/TTL to Differential PECL Translator
1630 S. STAPLEY DR., SUITE 127
MESA, ARIZONA 85204
USA
(480) 962-5881
FAX (480) 890-2541
www.azmicrotek.com
ARIZONA MICROTEK, INC.
PACKAGE AVAILABILITY
PART NUMBER
PACKAGE
MARKING
AZM10
ELT22
NOTES
SOIC 8
AZ10ELT22D
1,2,4
SOIC 8 RoHS
Compliant / Lead
(Pb) Free
AZ10ELT22D+
AZM10+
ELT22
1,2,4
SOIC 8
AZ100ELT22D
AZM100
ELT22
1,2,4
SOIC 8 RoHS
Compliant / Lead
(Pb) Free
AZ100ELT22D+
AZM100+
ELT22
1,2,4
TSSOP 8
AZ10ELT22T
AZT
LT22
1,2,4
TSSOP 8 RoHS
Compliant / Lead
(Pb) Free
AZ10ELT22T+
AZT+
LT22
1,2,4
TSSOP 8
AZ100ELT22T
AZH
LT22
1,2,4
TSSOP 8 RoHS
Compliant / Lead
(Pb) Free
1
Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts)
Tape & Reel.
2
Date code format: “Y” or “YY” for year followed by “WW” for week.
3
Parts marked JNB for date codes prior to 4WW (prior to 2004).
4
Date code “YWW” or “YYWW” on underside of part.
AZ100ELT22T+
AZH+
LT22
1,2,4
FEATURES
Green / RoHS Compliant /
Lead (Pb) Free package available
0.5ns Typical Propagation Delay
<100ps Typical Output to Output
Skew
Differential PECL Outputs
Flow Through Pinouts
Operating Range of 3.0V to 5.5V
Direct Replacement for
ON Semiconductor MC10ELT22 &
MC100ELT22
IBIS Model Files Available on
Arizona Microtek Website
DESCRIPTION
The AZ10/100ELT22 is a dual
CMOS/TTL
to
differential
translator. Because PECL (Positive ECL)
levels are used, only V
CC
and ground are
required. The small outline packaging and the low skew, dual gate design of the ELT22 makes it ideal for
applications that require the translation of a clock and a data signal.
The ELT22 is available in both PECL standards: the 10ELT is compatible with PECL 10K logic levels while
the 100ELT is compatible with PECL 100K logic levels.
NOTE: Specifications in PECL tables are valid when thermal equilibrium is established.
PECL
PIN DESCRIPTION
PIN
D0, D1
V
CC
GND
FUNCTION
Q0,
ˉˉ , Q1, ˉˉ
Differential PECL Outputs
CMOS/TTL Input
Positive Supply
Ground
LOGIC DIAGRAM AND
PINOUT
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PDF描述 |
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| AZ10ELT22D | CMOS/TTL to Differential PECL Translator |
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