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參數(shù)資料
| 型號： | AZ10EL31TR2 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | ECL/PECL D Flip-Flop with Set and Reset |
| 中文描述： | ECL / PECL的D觸發(fā)器的設(shè)置和復(fù)位 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大?。?/td> | 140K |
| 代理商： | AZ10EL31TR2 |
AZ10EL31
AZ100EL31
ECL/PECL D Flip-Flop with Set and Reset
1630 S. STAPLEY DR., SUITE 125
MESA, ARIZONA 85204
USA
(480) 962-5881
FAX (480) 890-2541
www.azmicrotek.com
ARIZONA MICROTEK, INC.
FEATURES
475ps Propagation Delay
2.8GHz Toggle Frequency
75k
Internal Input Pulldown Resistors
Direct Replacement for ON Semiconductor
MC10EL31 & MC100EL31
DESCRIPTION
The AZ10/100EL31 is a master-slave D flip-flop with set and reset. The device is functionally equivalent to the
E131 device with higher performance capabilities. With propagation delays and output transition times significantly
faster than the E131, the EL31 is ideally suited for those applications that require the ultimate in AC performance.
Both set and reset inputs are asynchronous, level triggered signals. Data enters the master section of the flip-
flop when the clock is LOW. When the clock transitions from LOW to HIGH, the data in the master section
transfers into the slave section and through to the outputs.
NOTE: Specifications in ECL/PECL tables are valid when thermal equilibrium is established.
V
CC
Positive Supply
V
EE
Negative Supply
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
8
5
6
7
4
3
2
1
VCC
D
VEE
S
Q
Q
R
S
D
R
Flip Flop
CLK
PACKAGE AVAILABILITY
PACKAGE
PART NO.
SOIC 8
AZ10EL31D
SOIC 8 T&R
AZ10EL31DR1
SOIC 8 T&R
AZ10EL31DR2
SOIC 8
AZ100EL31D
SOIC 8 T&R
AZ100EL31DR1 AZM100EL31
SOIC 8 T&R
AZ100EL31DR2 AZM100EL31
TSSOP 8
AZ10EL31T
TSSOP 8 T&R AZ10EL31TR1
TSSOP 8 T&R AZ10EL31TR2
TSSOP 8
AZ100EL31T
TSSOP 8 T&R AZ100EL31TR1
TSSOP 8 T&R AZ100EL31TR2
MARKING
AZM10EL31
AZM10EL31
AZM10EL31
AZM100EL31
AZTEL31
AZTEL31
AZTEL31
AZHEL31
AZHEL31
AZHEL31
TRUTH TABLE
D
L
H
X
X
X
S*
R*
CLK
Q
Q
L
L
H
L
H
L
L
L
H
H
Z
Z
X
X
X
L
H
H
L
H
L
L
H
Undef
Undef
Z = LOW to HIGH Transition
* Pins will default low when left open
PIN DESCRIPTION
PIN
Set Input
Data Input
Reset Input
CLK
Clock Input
Q, Q
Data Outputs
FUNCTION
S
D
R
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AZ10EL31D | ECL/PECL D Flip-Flop with Set and Reset |
| AZ10EL31DR1 | ECL/PECL D Flip-Flop with Set and Reset |
| AZ10EL31DR2 | ECL/PECL D Flip-Flop with Set and Reset |
| AZ10EL58 | ECL/PECL 2:1 Multiplexer |
| AZ100EL58D | ECL/PECL 2:1 Multiplexer |
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| AZ1117_12 | 制造商:BCDSEMI 制造商全稱:BCD Semiconductor Manufacturing Limited 功能描述:1A LOW DROPOUT LINEAR REGULATOR |
| AZ1117_13 | 制造商:BCDSEMI 制造商全稱:BCD Semiconductor Manufacturing Limited 功能描述:1A LOW DROPOUT LINEAR REGULATOR |
| AZ1117B | 制造商:BCDSEMI 制造商全稱:BCD Semiconductor Manufacturing Limited 功能描述:600mA LOW DROPOUT LINEAR REGULATOR |
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