- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄381547 > AZ100E142FN (Arizona Microtek, Inc.) ECL/PECL 9-bit Shift Register PDF資料下載
參數(shù)資料
| 型號(hào)： | AZ100E142FN |
| 廠商： | Arizona Microtek, Inc. |
| 英文描述： | ECL/PECL 9-bit Shift Register |
| 中文描述： | ECL / PECL的9位移位寄存器 |
| 文件頁(yè)數(shù)： | 1/5頁(yè) |
| 文件大?。?/td> | 82K |
| 代理商： | AZ100E142FN |
AZ10E142
AZ100E142
ECL/PECL 9-bit Shift Register
1630 S. STAPLEY DR., SUITE 127
MESA, ARIZONA 85204
USA
(480) 962-5881
FAX (480) 890-2541
www.azmicrotek.com
ARIZONA MICROTEK, INC.
FEATURES
700 MHz Minimum Shift Frequency
9-Bit for Byte-Parity Application
Asynchronous Master Reset
Dual Clocks
Operating Range of 4.2V to 5.46V
75k
Ω
Internal Input Pulldown Resistors
Direct Replacement for ON Semi
MC10E142 & MC100E142
DESCRIPTION
The AZ10/100E142 is a 9-bit shift register, designed with byte-parity applications in mind. The E142 performs
serial/parallel in and serial/parallel out, shifting in one direction. The nine inputs D0-D8 accept parallel input data,
while S-IN accepts serial input data. The Qn outputs do not need to be terminated for the shift operation to function.
To minimize noise and power, any Q output not used should be left unterminated.
The SEL (Select) input pin is used to switch between the two modes of operation
–
SHIFT and LOAD. The shift
direction is from bit 0 to bit 8. Input data is accepted by the registers a set-up time before the positive going edge of
CLK1 or CLK2; shifting is also accomplished on the positive clock edge. A HIGH on the Master Reset pin (MR)
asynchronously resets all the registers to zero.
NOTE: Specifications in ECL/PECL tables are valid when thermal equilibrium is established.
V
CCO
26
27
28
1
2
3
4
SEL
D8
D7
D6
V
CCO
D5
Q8
Q7
Q6
V
CC
Q5
V
CCO
Q4
Q3
Q2
Q1
Q0
D4
D3
D2
MR
CLK1
CLK2
V
EE
S-IN
D0
D1
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
Pinout: 28-lead
PLCC (top view)
PACKAGE AVAILABILITY
PART NUMBER
PACKAGE
MARKING
AZM10E142
<Date Code>
AZM100E142
<Date Code>
NOTES
PLCC 28
AZ10E142FN
1,2
PLCC 28
AZ100E142FN
1,2
1
2
Add R2 at end of part number for 13 inch (2.5K parts) Tape & Reel.
Date code format: “YY” for year followed by “WW” for week.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AZ10E142 | ECL/PECL 9-bit Shift Register |
| AZ10E142FN | ECL/PECL 9-bit Shift Register |
| AZ100EL01T | ECL/PECL 4-Input OR/NOR |
| AZ10EL01 | ECL/PECL 4-Input OR/NOR |
| AZ10EL01D | ECL/PECL 4-Input OR/NOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AZ100EL01 | 制造商:AZM 制造商全稱:AZM 功能描述:ECL/PECL 4-Input OR/NOR |
| AZ100EL01D | 制造商:AZM 制造商全稱:AZM 功能描述:ECL/PECL 4-Input OR/NOR |
| AZ100EL01T | 制造商:AZM 制造商全稱:AZM 功能描述:ECL/PECL 4-Input OR/NOR |
| AZ100EL07 | 制造商:AZM 制造商全稱:AZM 功能描述:ECL/PECL 2-Input XOR/XNOR |
| AZ100EL07D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ECL/PECL 2-Input XOR/XNOR |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。