
AZ10E131
AZ100E131
ECL/PECL 4-bit D Flip-Flop
1630 S. STAPLEY DR., SUITE 127
MESA, ARIZONA 85204
USA
(480) 962-5881
FAX (480) 890-2541
www.azmicrotek.com
ARIZONA MICROTEK, INC.
FEATURES
1100 MHz Min. Toggle Frequency
Differential Outputs
Individual and Common Clocks
Individual Resets (asynchronous)
Paired Sets (asynchronous)
Operating Range of 4.2V to 5.46V
75k
Ω
Internal Input Pulldown Resistors
Direct Replacement for On Semiconductor
MC10E131 & MC100E131
DESCRIPTION
The AZ10/100E131 is a quad master-slave D-type flip-flop with differential outputs. Each flip-flop may be
clocked separately by holding Common Clock (C
C
) LOW and using the Clock Enable (ˉˉ n) inputs for clocking.
Common clocking is achieved by holding the ˉˉ n inputs LOW and using C
C
to clock all four flip-flops. In this
case, the ˉˉ n inputs perform the function of controlling the common clock to each flip-flop.
Individual asynchronous resets are provided (Rn). Asynchronous set controls (Sn) are ganged together in pairs,
with the pairing chosen to reflect physical chip symmetry.
Data enters the master when both C
C
and ˉˉ n are LOW, and transfers to the slave when either C
C
or ˉˉ n (or
both) go HIGH.
NOTE: Specifications in ECL/PECL tables are valid when thermal equilibrium is established.
* All V
CC
and V
CCO
pins are tied together on the die.
26
27
28
1
2
3
4
V
CCO
V
CC
NC
V
CCO
V
EE
25
24
23
22
21
20
1918
17
16
15
14
13
12
11
10
9
8
7
6
5
R3
D2
CE2
R2
Q3
Q3
Q2
Q2
Q1
Q1
Q0
Q0
R1
CE1
D1
R0
CE0
D0
S03
C
C
S12
D3
CE3
Pinout: 28-Lead
PLCC (top view)
PACKAGE AVAILABILITY
PART NUMBER
PACKAGE
MARKING
AZM10E131
<Date Code>
AZM100E131
<Date Code>
NOTES
PLCC 28
AZ10E131FN
1,2
PLCC 28
AZ100E131FN
1,2
1
2
Add R2 at end of part number for 13 inch (2.5K parts) Tape & Reel.
Date code format: “YY” for year followed by “WW” for week.