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參數(shù)資料
| 型號： | AZ100E111 |
| 廠商： | Arizona Microtek, Inc. |
| 英文描述： | ECL/PECL 1:9 Differential Clock Driver |
| 中文描述： | ECL / PECL的1:9差分時鐘驅動器 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大小： | 99K |
| 代理商： | AZ100E111 |
AZ10E111
AZ100E111
ECL/PECL 1:9 Differential Clock Driver
1630 S. STAPLEY DR., SUITE 127
MESA, ARIZONA 85204
USA
(480) 962-5881
FAX (480) 890-2541
www.azmicrotek.com
ARIZONA MICROTEK, INC.
FEATURES
Low Skew
Differential Design
Clock Enable
V
BB
Output
Operating Range of 4.2V to 5.46V
75k
Ω
Internal Input Pulldown Resistors
Direct Replacement for ON Semi
MC10E111 & MC100E111
DESCRIPTION
The AZ10/100E111 is a low skew 1-to-9 differential driver, designed with clock distribution in mind. The IN
signal is fanned-out to nine identical differential outputs. An Enable input is also provided. A HIGH disables the
device by forcing all Q outputs LOW and all Q
outputs HIGH.
The AZ100E111 provides a V
BB
output for single-ended use or a DC bias reference for AC coupling to the
device. For single–ended input applications, the V
BB
reference should be connected to one side of the IN/ˉˉ
differential input pair. The input signal is then fed to the other IN/ˉˉ input. The V
bias for the E111 as its sink/source capability is limited. When used, the V
BB
pin should be bypassed to ground via a
0.01
μ
F capacitor.
The device is specifically designed, modeled and produced with low skew as the key goal. Optimal design and
layout serve to minimize gate-to-gate skew within-device, and empirical modeling is used to determine process
control limits that ensure consistent t
pd
distributions from lot-to-lot. The net result is a dependable, low skew device.
To ensure that the tight skew specification is met, both sides of the differential output must be terminated into
50
Ω
, even if only one side is used. In most applications all nine differential pairs will be used and therefore
terminated. In the case where fewer than nine pairs are used, it is necessary to terminate at least the output pairs on
the same package side (i.e. sharing the same V
CCO
) as the pair(s) being used on that side, in order to maintain
minimum skew. Failure to do this will result in small degradations of propagation delay (on the order of 10-20ps) of
the output(s) being used that, while not being catastrophic to most designs, will mean a loss of skew margin.
NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.
BB
pin should be used only as a
PACKAGE AVAILABILITY
PART NUMBER
PACKAGE
MARKING
AZM10E111
<Date Code>
AZM100E111
<Date Code>
NOTES
PLCC 28
AZ10E111FN
1,2
PLCC 28
AZ100E111FN
1,2
1
2
Add R2 at end of part number for 13 inch (2.5K parts) Tape & Reel.
Date code format: “YY” for year followed by “WW” for week.
相關PDF資料 |
PDF描述 |
|---|---|
| AZ100E111FN | ECL/PECL 1:9 Differential Clock Driver |
| AZ10E111 | ECL/PECL 1:9 Differential Clock Driver |
| AZ10E111FN | ECL/PECL 1:9 Differential Clock Driver |
| AZ100E116FN | ECL/PECL Quint Differential Line Receiver |
| AZ10E116 | ECL/PECL Quint Differential Line Receiver |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AZ100E111FN | 制造商:AZM 制造商全稱:AZM 功能描述:ECL/PECL 1:9 Differential Clock Driver |
| AZ100E116FN | 制造商:AZM 制造商全稱:AZM 功能描述:ECL/PECL Quint Differential Line Receiver |
| AZ100E131 | 制造商:AZM 制造商全稱:AZM 功能描述:ECL/PECL 4-bit D Flip-Flop |
| AZ100E131FN | 制造商:AZM 制造商全稱:AZM 功能描述:ECL/PECL 4-bit D Flip-Flop |
| AZ100E142 | 制造商:AZM 制造商全稱:AZM 功能描述:ECL/PECL 9-bit Shift Register |
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