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參數資料
| 型號： | AX88196 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 10/100BASE 3-in-1 Local CPU Bus Fast Ethernet Controller with Embedded SRAM |
| 中文描述： | 一個10/100Base 3合1本地CPU總線快速以太網控制器與嵌入式靜態(tài)存儲器 |
| 文件頁數： | 11/42頁 |
| 文件大小： | 594K |
| 代理商： | AX88196 |
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AX88196 Local CPU BUS MAC Controller
I/PD
124
Address Enable : The signal is asserted when the address bus is
available for DMA cycle. When negated (low), AX88196 an I/O slave
device may respond to addresses and I/O command.
PSEN : This signal is active low for 8051 program access. For I/O
device, AX88196, this signal is active high to access the chip. This
signal is for 8051 bus application only.
ASIX ELECTRONICS CORPORATION
11
AEN
or
/PSEN
Tab - 1 Local CPU bus interface signals group
2.2 MII interface signals group
SIGNAL
TYPE
I
PIN NO.
90 – 87
DESCRIPTION
RXD[3:0]
Receive Data : RXD[3:0] is driven by the PHY synchronously with
respect to RX_CLK.
Carrier Sense : Asynchronous signal CRS is asserted by the PHY
when either the transmit or receive medium is non-idle.
Receive Data Valid : RX_DV is driven by the PHY synchronously
with respect to RX_CLK. Asserted high when valid data is present on
RXD [3:0].
Receive Error : RX_ER ,is driven by PHY and synchronous to
RX_CLK, is asserted for one or more RX_CLK periods to indicate to
the port that an error has detected.
Receive Clock : RX_CLK is a continuous clock that provides the
timing reference for the transfer of the RX_DV,RXD[3:0] and
RX_ER signals from the PHY to the MII port of the repeater.
Collision : this signal is driven by PHY when collision is detected.
Transmit Enable : TX_EN is transition synchronously with respect to
the rising edge of TX_CLK. TX_EN indicates that the port is
presenting nibbles on TXD [3:0] for transmission.
Transmit Data : TXD[3:0] is transition synchronously with respect to
the rising edge of TX_CLK. For each TX_CLK period in which
TX_EN is asserted, TXD[3:0] are accepted for transmission by the
PHY.
Transmit Clock : TX_CLK is a continuous clock from PHY. It
provides the timing reference for the transfer of the TX_EN and
TXD[3:0] signals from the MII port to the PHY.
Station Management Data Clock : The timing reference for MDIO.
All data transfers on MDIO are synchronized to the rising edge of this
clock. MDC is a 2.5MHz frequency clock output.
Station Management Data Input / Output : Serial data input/output
transfers from/to the PHYs . The transfer protocol conforms to the
IEEE 802.3u MII specification.
CRS
I
85
RX_DV
I
83
RX_ER
I
82
RX_CLK
I
86
COL
TX_EN
I
84
95
O
TXD[3:0]
O
99 – 96
TX_CLK
I
94
MDC
O
92
MDIO
I/O/PU
91
Tab - 2 MII interface signals group
相關PDF資料 |
PDF描述 |
|---|---|
| AX88196L | 10/100BASE 3-in-1 Local CPU Bus Fast Ethernet Controller with Embedded SRAM |
| AX88796 | 3-in-1 Local Bus Fast Ethernet Controller |
| AX88796L | 3-in-1 Local Bus Fast Ethernet Controller |
| AY3-8910 | PROGRAMMABLE SOUND GENERATOR |
| AY-3-8910 | PROGRAMMABLE SOUND GENERATOR |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AX88196BLF | 制造商:ASIX 制造商全稱:ASIX 功能描述:Low-pin-count Non-PCI 8/16-bit 10/100M Fast Ethernet Controller with MII Interface |
| AX88196L | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10/100BASE 3-in-1 Local CPU Bus Fast Ethernet Controller with Embedded SRAM |
| AX88613 | 制造商:ASIX 制造商全稱:ASIX 功能描述:ASIX Multi-Port Ethernet Controller |
| AX88615 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:5-Port 10/100BASE Ethernet Switch |
| AX88615P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:5-Port 10/100BASE Ethernet Switch |
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