tDP
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� AX250-FG484
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 203/262闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA AXCELERATOR 250K 484FBGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 40
绯诲垪锛� Axcelerator
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 2816
RAM 浣嶇附瑷�(j矛)锛� 55296
杓稿叆/杓稿嚭鏁�(sh霉)锛� 248
闁€鏁�(sh霉)锛� 250000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 484-BGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 484-FPBGA锛�23x23锛�
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Axcelerator Family FPGAs
Re vi s i on 18
2 - 31
LVTTL Output Drive Strength = 2 (12 mA) / High Slew Rate
tDP
Input Buffer
1.68
1.92
2.26
ns
tPY
Output Buffer
3.30
3.76
4.42
ns
tENZL
Enable to Pad Delay through the Output Buffer鈥擹 to
Low
3.74
4.26
5.00
ns
tENZH
Enable to Pad Delay through the Output Buffer鈥擹 to
High
3.06
3.49
4.10
ns
tENLZ
Enable to Pad Delay through the Output Buffer鈥擫ow
to Z
1.89
1.91
ns
tENHZ
Enable to Pad Delay through the Output Buffer鈥擧igh
to Z
2.29
2.30
2.31
ns
tIOCLKQ
Sequential Clock-to-Q for the I/O Input Register
0.67
0.77
0.90
ns
tIOCLKY
Clock-to-output Y for the I/O Output Register and the
I/O Enable Register
0.67
0.77
0.90
ns
tSUD
Data Input Set-Up
0.23
0.27
0.31
ns
tSUE
Enable Input Set-Up
0.26
0.30
0.35
ns
tHD
Data Input Hold
0.00
ns
tHE
Enable Input Hold
0.00
ns
tCPWHL
Clock Pulse Width High to Low
0.39
ns
tCPWLH
Clock Pulse Width Low to High
0.39
ns
tWASYN
Asynchronous Pulse Width
0.37
ns
tREASYN
Asynchronous Recovery Time
0.13
0.15
0.17
ns
tHASYN
Asynchronous Removal Time
0.00
ns
tCLR
Asynchronous Clear-to-Q
0.23
0.27
0.31
ns
tPRESET
Asynchronous Preset-to-Q
0.23
0.27
0.31
ns
Table 2-22 3.3 V LVTTL I/O Module
Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70掳C (continued)
鈥�2 Speed
鈥�1 Speed
Std Speed
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max. Units
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