參數(shù)資料
型號(hào): AV3169
廠商: Electronic Theatre Controls, Inc.
英文描述: Video Encoder
中文描述: 視頻編碼器
文件頁(yè)數(shù): 9/24頁(yè)
文件大?。?/td> 196K
代理商: AV3169
AV3168/69
9-24
January 4, 2001
VIDEO TIMING GENERATION
The video encoder can operate as a master or a slave in the timing generation. In the master mode, the video
encoder outputs SYNC signals. In the slave mode, the internal timing is lock to the external SYNC signals.
MASTER MODE
If the MSTRpin is high, the video encoder operates in the master mode. It uses the internal counters to generate
the video timing and outputs HSYN and VSYN. The HSYNs are asserted for 64 pixel times. The negative transition
of the HSYNs occur in the Cb slot.
The VSYNs are asserted for 3 line times for NTSC and 2.5 for PAL. The co-incident negative transitions of HSYN
and VSYN indicate the beginning of an odd field. The negative transition of the VSYN while the HSYN is high
indicates the beginning of an even field.
SLAVE MODE
In the slave mode operation, the decoder automatically detects the input format and locks the internal timing
counters to the external synchronization signals. It support 2 types of synch inputs: (a) HSYN / VSYNC, or (b)
CCIR656 EAV data.
If EAV is present, the video encoder synchronized to the EAV packets according to CCIR656 specifications to
generate the video timing. HSYN and VSYN signals are ignored.
If EAV is not present, the Video Encoder uses the signals presented on HSYN and VSYN for line and field counter
increment. If register CR0[3] is low the encoder assumes the negative transition of the HSYN should be co-incited
with the Cb0 datum. If CR0[3] is high it assume the transition co-incited with Y0 datum.
VSYN
VSYN
Blanked
273 - 280
524
NTSC VERTICAL INTERVAL TIMING
10 - 20
Field One
Field Two
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525
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