參數(shù)資料
型號: AV3168
廠商: Electronic Theatre Controls, Inc.
英文描述: Video Encoder
中文描述: 視頻編碼器
文件頁數(shù): 14/24頁
文件大?。?/td> 196K
代理商: AV3168
AV3168/69
14-24
January 4, 2001
CONTROL and CLOSED CAPTION REGISTER DESCRIPTION
The AV3168 contains three 8-bit registers for timing generation, luma and chroma processing control, clock
generation and power management. Additionally it contains 4 Closed Caption Data Registers. These registers are
programmed via the 7-bit address I
2
C bus. I
2
C Address = 0X65. (I2C bus Address = 0x64 for AV3169). The
protocol is 7- bit chip address followed by 8- bit register address and 8-bit register data.
Control Register 0, CR0
(Address: 0x0, Default Value: 0x00)
Item
Register
Bits
Mnemonic
#bits
Description
1
CR0[7:6]
FSEL[1:0]
2
Chroma Filter Selection
00: Automatic bandwidth assignment based on
the output format selection (default)
01: 0.675 MHz bandwidth
10: 1.36 MHz bandwidth
11: 2 MHz bandwidth
2
CR0[5:4]
CMOD[1:0]
2
Component Output Selection. Valid only If pin 27
CPNT pin is ‘1’.
00: Sony Betacam (Default)
01: Mashushita M-II
10: SMPTE
11: RGB
3
CR0[3]
SDLY
1
Input Hsyn negative transition position
0: The Negative HSYNC transition coincided
with Cb
0
datum (Default)
1: The Negative HSYNC transition co-incited
with Y
0
datum.
4
CR0[2]
SCH
1
Subcarrier horizontal sync phase control (SCH)
0: Subcarrier reset every 4 fields for NTSC and
every 8 field for PAL (Default), SCH =0
according CCIR 624 Spec.
1: Subcarrier free running.
5
CR0[1]
PALMN
1
Enable South American PALM and PALN
0: Non-South American Mode, PAL(BDGHI),
or NTSC (Default).
1: South American Mode (Pal-M, Pal-N)
6
CR0[0]
FMT0
1
Used in master mode only to select either 525 or
625 line system timing.
0: 525-line M system (Default)
1: 626-line system.
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