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參數(shù)資料
| 型號： | AV1416D |
| 廠商： | Aplus Integrated Circuits Inc. |
| 英文描述： | ER 6C 4#16 2#8 SKT PLUG |
| 中文描述： | 單芯片CMOS VLSI的合成 |
| 文件頁數(shù)： | 8/10頁 |
| 文件大?。?/td> | 364K |
| 代理商： | AV1416D |
AVxx16K
Series
9. TIMING DIAGRAM:
Rev 1.1 2003/9/18
7
Edge Trigger
Tw
Tw
Sub_table N
Sub_table N
OKY/IO1/IO2
AUDIO
AUDIO
Level Trigger
Tw
Sub_table N
AUDIO
Sub_table N
AUDIO
Sub_table N
Sub_table N
Tw
Edge Trigger
Level Trigger
1.> Edge/Level
Level Mode:
Edge Mode:
* Note: Tw is the minimum pulse width > debounce time (5.3ms or 20.8us at 6kHz).
TG1/SC
OKY/IO1/IO2
OKY/IO1/IO2
Sub_table N
OKY/IO1/IO2
AUDIO
Sub_table N
AUDIO
2.> Hold/Unhold
Unhold:
Hold:
* Note: Both Edge and Level have Hold and Unhold option.
OKY/IO1/IO2
Sub_table N
AUDIO
3.> Retrigger/Irretrigger
Irretrigger:
Retrigger:
Play from beginning immediately.
Sub_table N
Sub_table N
AUDIO
Sub_table N
Sub_table N
Ignore trigger input signal during playing.
OKY/IO1/IO2
OKY/IO1/IO2
Voice
AUDIO
Stop_High pulse
LED 3Hz/6Hz flash
4.> Status Output (IO1/IO2)
Busy_High active
Busy_Low active
LED ON means status output low.
Mute
3Hz or 6Hz for playing speed at 6kHz
172ms at 6kHz
LED dynamic 2/4 :
When the voice amplitude is higher than 2/4 full-scale amplitude, LED ON.
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