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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | ATTINY44V-10MU |
| 寤犲晢锛� | Atmel |
| 鏂囦欢闋佹暩(sh霉)锛� | 45/238闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC MCU AVR 4K FLASH 10MHZ 20-QFN |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 490 |
| 绯诲垪锛� | AVR® ATtiny |
| 鏍稿績铏曠悊鍣細 | AVR |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 10MHz |
| 閫ｉ€氭€э細 | USI |
| 澶栧湇瑷�(sh猫)鍌欙細 | 娆犲妾㈡脯/寰�(f霉)浣�锛孭OR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 12 |
| 绋嬪簭瀛樺劜鍣ㄥ閲忥細 | 4KB锛�2K x 16锛� |
| 绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 | 闁冨瓨 |
| EEPROM 澶у皬锛� | 256 x 8 |
| RAM 瀹归噺锛� | 256 x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 1.8 V ~ 5.5 V |
| 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� | A/D 8x10b |
| 鎸暕鍣ㄥ瀷锛� | 鍏�(n猫i)閮� |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 20-WFQFN 瑁搁湶鐒婄洡 |
| 鍖呰锛� | 鎵樼洡 |
| 閰嶇敤锛� | ATAVRISP2-ND - PROGRAMMER AVR IN SYSTEM |
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2001 Microchip Technology Inc.
DS39026C-page 137
PIC18CXX2
14.4.6
I2C MASTER MODE START
CONDITION TIMING
To initiate a START condition, the user sets the START
condition enable bit, SEN (SSPCON2<0>). If the SDA
and SCL pins are sampled high, the baud rate genera-
tor is reloaded with the contents of SSPADD<6:0> and
starts its count. If SCL and SDA are both sampled high
when the baud rate generator times out (TBRG), the
SDA pin is driven low. The action of the SDA being
driven low, while SCL is high, is the START condition
and causes the S bit (SSPSTAT<3>) to be set. Follow-
ing this, the baud rate generator is reloaded with the
contents of SSPADD<6:0> and resumes its count.
When the baud rate generator times out (TBRG), the
SEN bit (SSPCON2<0>) will be automatically cleared
by hardware, the baud rate generator is suspended
leaving the SDA line held low and the START condition
is complete.
14.4.6.1
WCOL Status Flag
If the user writes the SSPBUF when a START
sequence is in progress, the WCOL is set and the con-
tents of the buffer are unchanged (the write doesn鈥檛
occur).
FIGURE 14-16:
FIRST START BIT TIMING
Note:
If, at the beginning of the START condition,
the SDA and SCL pins are already sam-
pled low, or if during the START condition,
the SCL line is sampled low before the
SDA line is driven low, a bus collision
occurs, the Bus Collision Interrupt Flag,
BCLIF is set, the START condition is
aborted, and the I2C module is reset into its
IDLE state.
Note:
Because
queueing
of
events
is
not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the START
condition is complete.
SDA
SCL
S
TBRG
1st Bit
2nd Bit
TBRG
SDA = 1,
At completion of START bit,
SCL = 1
Write to SSPBUF occurs here
TBRG
Hardware clears SEN bit
TBRG
Write to SEN bit occurs here.
Set S bit (SSPSTAT<3>)
and sets SSPIF bit
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