
96
32015G–AVR32–09/09
AT32AP7001
11.5.3.2
Lock suppression
When using high division or multiplication factors, there is a possibility that the PLL can give
false lock indications while sweeping to the correct frequency. To prevent false lock indications
from setting the LOCKn flag, the lock indication can be suppressed for a number of slow clock
cycles indicated in the PLLn:COUNT field. Typical start-up times can be found using the Atmel
filter caluclator (see below).
11.5.3.3
Operating range selection
To use PLLn, a passive RC filter should be connected to the LFTn pin, as shown in 
Figure 11-2.Filter values depend on the PLL reference and output frequency range. Atmel provides a tool
named “Atmel PLL LFT Filter Calculator AT91”. The PLL for AT32AP7001 can be selected in
this tool by selecting “AT91RM9200 (58A07F)” and leave “Icp = ‘1’” (default).
11.5.4
Synchronous clocks
Oscillator 0 (default) or PLL0 provides the source for the main clocks, which is the common root
for the synchronous clocks for the CPU, and HSB, PBA, and PBB modules. The main clock is
divided by an 8-bit prescaler, and each of these four synchronous clocks can run from any tap-
ping of this prescaler, or the undivided main clock, as long as f
CPU
f
HSB
f
PBx and fPBB=fHSB.
The synchronous clock source can be changed on-the fly, responding to varying load in the
application. The clock domains can be shut down in sleep mode, as described in 
”Sleep modes”on page 99. Additionally, the clocks for each module in the four domains can be individually
 masked, to avoid power consumption in inactive modules.
Figure 11-3. Synchronous clock generation
Mask
Prescaler
0
1
Osc0 clock
PLL0 clock
PLLSEL
0
1
CPUSEL
CPUDIV
Main clock
Sleep
Controller
CPUMASK
CPU clocks
HSB clocks
PBAclocks
PBB clocks
Sleep
instruction