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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� ATTINY44A-SSF
寤犲晢锛� Atmel
鏂囦欢闋佹暩(sh霉)锛� 105/135闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC MCU 8BIT 4KB FLASH 14SOIC
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� MCU Product Line Introduction
tinyAVR Introduction
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 98
绯诲垪锛� AVR® ATtiny
鏍稿績铏曠悊鍣細 AVR
鑺珨灏哄锛� 8-浣�
閫熷害锛� 20MHz
閫ｉ€氭€э細 USI
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杓稿叆/杓稿嚭鏁�(sh霉)锛� 12
绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲忥細 4KB锛�2K x 16锛�
绋嬪簭瀛樺劜(ch菙)鍣ㄩ鍨嬶細 闁冨瓨
EEPROM 澶�?銆�?/td> 256 x 8
RAM 瀹归噺锛� 256 x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 1.8 V ~ 5.5 V
鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� A/D 8x10b
鎸暕鍣ㄥ瀷锛� 鍏�(n猫i)閮�
宸ヤ綔婧害锛� -40°C ~ 125°C
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MB91470/480 Series
70
(6) Normal Bus Access Read/Write Operation
(VCC
= 4.0 V to 5.5 V, VSS = AVSS10 = AVSS12 = 0.0 V, TA = 40 掳C to + 85 掳C)
(Continued)
Parameter
Symbol
Pin Name
Condi-
tion
Value
Unit Remarks
Min
Max
ASX setup
tASLCH
SYSCLK
ASX
3
ns
ASX hold
tCHASH
31/2
脳 tCYC + 10 ns
CS0X to CS2X setup
tCSLCH
SYSCLK
CS0X to CS2X
3
ns
CS0X to CS2X hold
tCHCSH
31/2
脳 tCYC + 10 ns
Address setup
tASCH
SYSCLK
A15 to A00
3
ns
tASRL
RDX
A15 to A00
3
ns
tASWL
WR0X, WR1X
A15 to A00
3
ns
Address hold
tCHAX
SYSCLK
A15 to A00
31/2
脳 tCYC + 10 ns
tRHAX
RDX
A15 to A00
3
ns
tWHAX
WR0X, WR1X
A15 to A00
3
ns
Valid address
鈫�
Valid data input time
tAVDV
A15 to A00
D31 to D16
3/2
脳 tCYC 7ns
*1
*2
RDX delay time
tCHRL
SYSCLK
RDX
10
ns
tCHRH
10
ns
RDX
鈫� 鈫�
Valid data input time
tRLDV
RDX
D31 to D16
tCYC
5ns *1
Data setup
鈫�
RDX
鈫� time
tDSRH
18
ns
RDX
鈫� 鈫�
Data hold time
tRHDX
0
ns
RDX minimum pulse width
tRLRH
RDX
tCYC
5
ns
WR0X, WR1X delay time
tCHWL
SYSCLK
RDX
10
ns
tCHWH
10
ns
Data setup
鈫�
WR0X, WR1X
鈫� time
tDSWH
WR0X, WR1X
D31 to D16
tCYC
ns
WR0X, WR1X
鈫� 鈫�
Data hold time
tWHDX
3
ns
WR0X, WR1X minimum pulse
width
tWLWH
WR0X, WR1X
tCYC
5
ns
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
516-230-356 CONN COVER PLASTIC 56POS SIDE
ATTINY84A-SSU IC MCU 8BIT 8K FLASH 14SOIC
516-230-256 CONN COVER PLASTIC 56POS TOP
ATTINY2313A-SU IC MCU AVR 2K FLASH 20MHZ 20SOIC
ATTINY24A-MF MCU AVR 2KB FLASH 20MHZ 20QFN
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
ATTINY44A-SSFR 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 4KB FL 256B EE 256B SRAM 20MHz Hi +125C RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT
ATTINY44A-SSN 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 4K FLASH 256B EE 256B SRAM - 20MHz RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT
ATTINY44A-SSNR 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU AVR 4KB FL 256B EE 256B SRAM 20MHz 105C RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT
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*鍨嬭櫉(h脿o) *鏁�(sh霉)閲� 寤犲晢 鎵硅櫉(h脿o) 灏佽
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