參數(shù)資料
型號(hào)： ATTINY43U-MU
廠商： Atmel
文件頁數(shù)： 62/158頁
文件大小： 0K
描述： MCU AVR 4K FLASH 8MHZ 20-QFN
產(chǎn)品培訓(xùn)模塊： ATtiny43U Overview
MCU Product Line Introduction
tinyAVR Introduction
標(biāo)準(zhǔn)包裝： 490
系列： AVR® ATtiny
核心處理器： AVR
芯體尺寸： 8-位
速度： 8MHz
連通性： USI
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，POR，PWM，溫度傳感器，WDT
輸入/輸出數(shù)： 16
程序存儲(chǔ)器容量： 4KB（2K x 16）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 64 x 8
RAM 容量： 256 x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 20-WFQFN 裸露焊盤
包裝： 托盤
產(chǎn)品目錄頁面： 613 (CN2011-ZH PDF)
配用： ATSTK600-TINYX3U-ND - STK600 SOCKET/ADAPTER TINYX3U
154
8048C–AVR–02/12
ATtiny43U
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming
operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase
instruction. The Chip Erase operation turns the content of every memory location in both the
Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods
for the serial clock (SCK) input are defined as follows:
Low:> 2 CPU clock cycles for f
ck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz
High:> 2 CPU clock cycles for f
ck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz
19.7.1
Serial Programming Algorithm
When writing serial data to the ATtiny43U, data is clocked on the rising edge of SCK.
When reading data from the ATtiny43U, data is clocked on the falling edge of SCK. See Figure
20-8 and Figure 20-9 for timing details.
To program and verify the ATtiny43U in the Serial Programming mode, the following sequence
is recommended (see four byte instruction formats in Table 19-16):
1.
Power-up sequence:
Apply power between V
CC and GND while RESET and SCK are set to “0”. In some sys-
tems, the programmer can not guarantee that SCK is held low during power-up. In this
case, RESET must be given a positive pulse of at least two CPU clock cycles duration
after SCK has been set to “0”. The duration of the pulse must be at least t
RST plus two
CPU clock cycles. See Table 20-4 on page 161 for definition of minimum pulse width
on RESET pin, t
RST
2.
Wait for at least 20 ms and enable serial programming by sending the Programming
Enable serial instruction to pin MOSI.
3.
The serial programming instructions will not work if the communication is out of syn-
chronization. When in sync. the second byte (0x53), will echo back when issuing the
third byte of the Programming Enable instruction. Whether the echo is correct or not, all
four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give
RESET a positive pulse and issue a new Programming Enable command.
4.
The Flash is programmed one page at a time. The memory page is loaded one byte at
a time by supplying the 5 LSB of the address and data together with the Load Program
memory Page instruction. To ensure correct loading of the page, the data low byte must
be loaded before data high byte is applied for a given address. The Program memory
Page is stored by loading the Write Program memory Page instruction with the 3 MSB
of the address. If polling (RDY/BSY) is not used, the user must wait at least t
WD_FLASH
before issuing the next page. (See Table 19-15 on page 155.) Accessing the serial pro-
gramming interface before the Flash write operation completes can result in incorrect
programming.
5.
A: The EEPROM array is programmed one byte at a time by supplying the address and
data together with the appropriate Write instruction. An EEPROM memory location is
first automatically erased before new data is written. If polling (RDY/BSY) is not used,
the user must wait at least t
WD_EEPROM before issuing the next byte. (See Table 19-15
on page 155.) In a chip erased device, no 0xFFs in the data file(s) need to be pro-
grammed.
B: The EEPROM array is programmed one page at a time. The Memory page is loaded
one byte at a time by supplying the 2 LSB of the address and data together with the
Load EEPROM Memory Page instruction. The EEPROM Memory Page is stored by
相關(guān)PDF資料
PDF描述
ATSAM3N00BA-AU IC MCU 16KB CORTEX-M3 64-LQFP
ATTINY28L-4AU IC MCU AVR 2K FLASH 4MHZ 32-TQFP
ATTINY28L-4MU IC MCU AVR 2K 2.7V 4MHZ 32-QFN
ATTINY28V-1MU IC MCU AVR 2K 1.8V 1.2MHZ 32-QFN
ATTINY84-20SSU MCU AVR 8K ISP FLASH 2.7V 14SOIC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ATTINY43U-MUR 功能描述:8位微控制器 -MCU 4KB FLSH 64B EE 256B SRAM-8MHz, IND 0.9V RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
ATTINY43U-SU 功能描述:8位微控制器 -MCU AVR 4KB, 64B EE 8MHz 256B SRAM, 0.9V RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
ATTINY43U-SUR 功能描述:8位微控制器 -MCU 4KB FLSH 64B EE 256B SRAM-8MHz, IND 0.9V RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
ATTINY44 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash
ATTINY44-15MZ 功能描述:8位微控制器 -MCU 4KB Flash 15MHz Auto 125-degrees C RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*