參數(shù)資料
型號: ATTINY28V-1PI
廠商: Atmel
文件頁數(shù): 7/13頁
文件大?。?/td> 0K
描述: IC AVR MCU 2K 1.2MHZ 1.8V 28DIP
標(biāo)準(zhǔn)包裝: 20
系列: AVR® ATtiny
核心處理器: AVR
芯體尺寸: 8-位
速度: 1.2MHz
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 11
程序存儲器容量: 2KB(1K x 16)
程序存儲器類型: 閃存
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-DIP(0.300",7.62mm)
包裝: 管件
3
ATtiny28L/V
1062FS–AVR–07/06
rupt on low-level input feature enables the ATtiny28 to be highly responsive to external
events, still featuring the lowest power consumption while in the power-down modes.
The device is manufactured using Atmel’s high-density, nonvolatile memory technology.
By combining an enhanced RISC 8-bit CPU with Flash on a monolithic chip, the Atmel
ATtiny28 is a powerful microcontroller that provides a highly flexible and cost-effective
solution to many embedded control applications. The ATtiny28 AVR is supported with a
full suite of program and system development tools including: macro assemblers, pro-
gram debugger/simulators, in-circuit emulators and evaluation kits.
Pin Descriptions
VCC
Supply voltage pin.
GND
Ground pin.
Port A (PA3..PA0)
Port A is a 4-bit I/O port. PA2 is output-only and can be used as a high-current LED
driver. At V
CC = 2.0V, the PA2 output buffer can sink 25 mA. PA3, PA1 and PA0 are
bi-directional I/O pins with internal pull-ups (selected for each bit). The port pins are tri-
stated when a reset condition becomes active, even if the clock is not running.
Port B (PB7..PB0)
Port B is an 8-bit input port with internal pull-ups (selected for all Port B pins). Port B
pins that are externally pulled low will source current if the pull-ups are activated.
Port B also serves the functions of various special features of the ATtiny28 as listed on
page 27. If any of the special features are enabled, the pull-up(s) on the corresponding
pin(s) is automatically disabled. The port pins are tri-stated when a reset condition
becomes active, even if the clock is not running.
Port D (PD7..PD0)
Port D is an 8-bit I/O port. Port pins can provide internal pull-up resistors (selected for
each bit). The port pins are tri-stated when a reset condition becomes active, even if the
clock is not running.
XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier.
RESET
Reset input. An external reset is generated by a low level on the RESET pin. Reset
pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter
pulses are not guaranteed to generate a reset.
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