6. Updated DC Characteristics for VOL, I
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� ATTINY26L-8MI
寤犲晢锛� Atmel
鏂囦欢闋佹暩(sh霉)锛� 8/18闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC AVR MCU 2K LV 8MHZ IND 32-QFN
妯欐簴鍖呰锛� 490
绯诲垪锛� AVR® ATtiny
鏍稿績铏曠悊鍣細 AVR
鑺珨灏哄锛� 8-浣�
閫熷害锛� 8MHz
閫i€氭€э細 USI
澶栧湇瑷�(sh猫)鍌欙細 娆犲妾㈡脯/寰�(f霉)浣�锛孭OR锛孭WM锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 16
绋嬪簭瀛樺劜鍣ㄥ閲忥細 2KB锛�1K x 16锛�
绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 闁冨瓨
EEPROM 澶�?銆�?/td> 128 x 8
RAM 瀹归噺锛� 128 x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 2.7 V ~ 5.5 V
鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� A/D 11x10b
鎸暕鍣ㄥ瀷锛� 鍏�(n猫i)閮�
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 32-VFQFN 瑁搁湶鐒婄洡
鍖呰锛� 鎵樼洡
16
1477KS鈥揂VR鈥�08/10
ATtiny26(L)
6. Updated DC Characteristics for VOL, IIL, IIH, ICC Power Down and VACIO in 鈥淓lectrical
Characteristics鈥� on page 126.
7. Updated VINT, INL and Gain Error in 鈥淎DC Characteristics鈥� on page 129 and page 130.
Fixed typo in 鈥淎bsolute Accuracy鈥� on page 130.
8. Added Figure 106 in 鈥淧in Driver Strength鈥� on page 146, Figure 120, Figure 121 and
Figure 122 in 鈥淏OD Thresholds and Analog Comparator Offset鈥� on page 155. Updated
Figure 117 and Figure 118.
9. Removed LPM Rd, Z+ from 鈥淚nstruction Set Summary鈥� on page 169. This instruction
is not supported in ATtiny26.
Rev. 1477D-05/03
1. Updated 鈥淧ackaging Information鈥� on page 172.
2. Removed ADHSM from 鈥淎DC Characteristics鈥� on page 129.
3. Added section 鈥淓EPROM Write During Power-down Sleep Mode鈥� on page 20.
4. Added section 鈥淒efault Clock Source鈥� on page 26.
5. Corrected PLL Lock value in the 鈥淏it 0 鈥� PLOCK: PLL Lock Detector鈥� on page 73.
6. Added information about conversion time when selecting differential channels on
page 97.
7. Corrected {DDxn, PORTxn} value on page 42.
8. Added section 鈥淯nconnected Pins鈥� on page 46.
9. Added note for RSTDISBL Fuse in Table 50 on page 108.
10. Corrected DATA value in Figure 61 on page 116.
11. Added WD_FUSE period in Table 60 on page 123.
12. Updated 鈥淎DC Characteristics鈥� on page 129 and added Table 66, 鈥淎DC Characteris-
tics, Differential Channels, TA = -40掳C to +85掳C,鈥� on page 130.
13. Updated 鈥淎Ttiny26 Typical Characteristics鈥� on page 131.
14. Added LPM Rd, Z and LPM Rd, Z+ in 鈥淚nstruction Set Summary鈥� on page 169.
Rev. 1477C-09/02
1. Changed the Endurance on the Flash to 10,000 Write/Erase Cycles.
Rev. 1477B-04/02
1. Removed all references to Power Save sleep mode in the section 鈥淪ystem Clock and
Clock Options鈥� on page 23.
2. Updated the section 鈥淎nalog to Digital Converter鈥� on page 94 with more details on
how to read the conversion result for both differential and single-ended conversion.
3. Updated 鈥淥rdering Information鈥� on page 171 and added QFN/MLF package
information.
Rev. 1477A-03/02
1. Initial version.
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
17FMN-SMT-A-TF CONN FMN HOUSING 17POS SIDE SMD
ATTINY26L-8MC IC AVR MCU 2K LV 8MHZ COM 32-QFN
ATTINY26-16SI IC AVR MCU 2K 16MHZ IND 20-SOIC
ATTINY26-16SC IC AVR MCU 2K 16MHZ COM 20-SOIC
ATTINY26-16PI IC AVR MCU 2K 16MHZ IND 20-DIP
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鍙冩暩(sh霉)鎻忚堪
ATTINY26L-8MISL383 鍒堕€犲晢:Atmel Corporation 鍔熻兘鎻忚堪:AVR, 2K FLASH, 128B EE, 128B S
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ATtiny26L-8PC 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU AVR 2K FLSH 128B EE 128B SRAM ADC 3V RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰ㄦ牸:SMD/SMT
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