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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | ATTINY261A-SUR |
| 寤犲晢锛� | Atmel |
| 鏂囦欢闋佹暩(sh霉)锛� | 63/296闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | MCU AVR 2KB FLASH 20MHZ 20SOIC |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | tinyAVR Introduction |
| 妯欐簴鍖呰锛� | 1,000 |
| 绯诲垪锛� | AVR® ATtiny |
| 鏍稿績铏曠悊鍣細 | AVR |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 20MHz |
| 閫ｉ€氭€э細 | USI |
| 澶栧湇瑷�(sh猫)鍌欙細 | 娆犲妾㈡脯/寰�(f霉)浣�锛孭OR锛孭WM锛屾韩搴﹀偝鎰熷櫒锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 16 |
| 绋嬪簭瀛樺劜鍣ㄥ閲忥細 | 2KB锛�1K x 16锛� |
| 绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 | 闁冨瓨 |
| EEPROM 澶�?銆�?/td> | 128 x 8 |
| RAM 瀹归噺锛� | 128 x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 1.8 V ~ 5.5 V |
| 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� | A/D 11x10b |
| 鎸暕鍣ㄥ瀷锛� | 鍏�(n猫i)閮� |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 20-SOIC锛�0.295"锛�7.50mm 瀵級 |
| 鍖呰锛� | 甯跺嵎 (TR) |
| 鍏跺畠鍚嶇ū锛� | ATTINY261A-SUR-ND ATTINY261A-SURTR |
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2000 Microchip Technology Inc.
Advanced Information
DS30475A-page 155
PIC18CXX8
15.4.7
I2C MASTER MODE REPEATED START
CONDITION TIMING
A Repeated START condition occurs when the RSEN
bit (SSPCON2 register) is programmed high and the
I2C logic module is in the IDLE state. When the RSEN
bit is set, the SCL pin is asserted low. When the SCL
pin is sampled low, the baud rate generator is loaded
with the contents of SSPADD<5:0> and begins count-
ing. The SDA pin is released (brought high) for one
baud rate generator count (TBRG). When the baud rate
generator times out, if SDA is sampled high, the SCL
pin will be de-asserted (brought high). When SCL is
sampled high, the baud rate generator is re-loaded with
the contents of SSPADD<6:0> and begins counting.
SDA and SCL must be sampled high for one TBRG.
This action is then followed by assertion of the SDA pin
(SDA = 0) for one TBRG, while SCL is high. Following
this, the RSEN bit (SSPCON2 register) will be automat-
ically cleared and the baud rate generator will not be
reloaded, leaving the SDA pin held low. As soon as a
START condition is detected on the SDA and SCL pins,
the S bit (SSPSTAT register) will be set. The SSPIF bit
will not be set until the baud rate generator has
timed-out.
Immediately following the SSPIF bit getting set, the
user may write the SSPBUF with the 7-bit address in
7-bit mode, or the default first address in 10-bit mode.
After the first eight bits are transmitted and an ACK is
received, the user may then transmit an additional
eight bits of address (10-bit mode) or eight bits of data
(7-bit mode).
15.4.7.1
WCOL Status Flag
If the user writes the SSPBUF when a Repeated
START sequence is in progress, the WCOL is set and
the contents of the buffer are unchanged (the write
doesn鈥檛 occur).
FIGURE 15-14: REPEAT START CONDITION WAVEFORM
Note 1: If RSEN is programmed while any other
event is in progress, it will not take effect.
2: A bus collision during the Repeated
START condition occurs if:
SDA is sampled low when SCL goes
from low to high.
SCL goes low before SDA is
asserted low. This may indicate that
another master is attempting to
transmit a data "1".
Note:
Because
queueing
of
events
is
not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
START condition is complete.
SDA
SCL
Sr = Repeated START
Write to SSPCON2
Write to SSPBUF occurs here.
Falling edge of ninth clock
End of Xmit
At completion of START bit,
hardware clear RSEN bit
1st Bit
Set S (SSPSTAT<3>)
TBRG
SDA = 1,
SCL(no change)
SCL = 1
occurs here.
TBRG
and set SSPIF
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| 5-583649-2 | CONT.CRP.SNAP TW.LF.STRIP |
| PCA9539RBS,118 | IC I/O EXPANDER I2C 16B 24HVQFN |
| PCA9539PW,112 | IC I/O EXPANDER I2C 16B 24TSSOP |
| PCA9698BS,118 | IC I/O EXPANDER I2C 40B 56HVQFN |
| PCA9555D,112 | IC I/O EXPANDER I2C 16B 24SOIC |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| ATTINY261A-XU | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 2K Flash;125B EEPROM 128B SRAM;16 IO Pins RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰ㄦ牸:SMD/SMT |
| ATTINY261A-XUR | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU AVR 2KB FLSH 128B EE 128B SRAM-20MHz, IND RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰ㄦ牸:SMD/SMT |
| ATTINY261-ESMZ | 鍒堕€犲晢:ATMEL 鍒堕€犲晢鍏ㄧū:ATMEL Corporation 鍔熻兘鎻忚堪:8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash |
| ATTINY261-ESSZ | 鍒堕€犲晢:ATMEL 鍒堕€犲晢鍏ㄧū:ATMEL Corporation 鍔熻兘鎻忚堪:8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash |
| ATTINY261-ESXZ | 鍒堕€犲晢:ATMEL 鍒堕€犲晢鍏ㄧū:ATMEL Corporation 鍔熻兘鎻忚堪:8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash |
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