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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | ATTINY24A-SSF |
| 寤犲晢锛� | Atmel |
| 鏂囦欢闋佹暩(sh霉)锛� | 121/135闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC MCU 8BIT 2KB FLASH 14SOIC |
| 鐢�(ch菐n)鍝佸煿瑷撴ā濉婏細 | MCU Product Line Introduction tinyAVR Introduction |
| 妯欐簴鍖呰锛� | 98 |
| 绯诲垪锛� | AVR® ATtiny |
| 鏍稿績铏曠悊鍣細 | AVR |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 20MHz |
| 閫ｉ€氭€э細 | USI |
| 澶栧湇瑷倷锛� | 娆犲妾㈡脯/寰╀綅锛孭OR锛孭WM锛屾韩搴﹀偝鎰熷櫒锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 12 |
| 绋嬪簭瀛樺劜鍣ㄥ閲忥細 | 2KB锛�1K x 16锛� |
| 绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 | 闁冨瓨 |
| EEPROM 澶�?銆�?/td> | 128 x 8 |
| RAM 瀹归噺锛� | 128 x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 1.8 V ~ 5.5 V |
| 鏁�(sh霉)鎿�(j霉)杞夋彌鍣細 | A/D 8x10b |
| 鎸暕鍣ㄥ瀷锛� | 鍏�(n猫i)閮� |
| 宸ヤ綔婧害锛� | -40°C ~ 125°C |
| 灏佽/澶栨锛� | 14-SOIC锛�0.154"锛�3.90mm 瀵級 |
| 鍖呰锛� | 绠′欢 |
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86
32015G鈥揂VR32鈥�09/09
AT32AP7001
10.8
Peripheral overview
10.8.1
External Bus Interface
Optimized for Application Memory Space support
Integrates Three External Memory Controllers:
鈥� Static Memory Controller
鈥� SDRAM Controller
鈥� ECC Controller
Additional Logic for NAND Flash/SmartMediaTM and CompactFlashTM Support
鈥� SmartMedia support: 8-bit as well as 16-bit devices are supported
鈥� CompactFlash support: all modes (Attribute Memory, Common Memory, I/O, True IDE) are
supported but the signals _IOIS16 (I/O and True IDE modes) and _ATA SEL (True IDE mode)
are not handled.
Optimized External Bus:
鈥� 16- or 32-bit Data Bus
鈥� Up to 26-bit Address Bus, Up to 64-Mbytes Addressable
鈥� Optimized pin multiplexing to reduce latencies on External Memories
Up to 6 Chip Selects, Configurable Assignment:
鈥� Static Memory Controller on NCS0
鈥� SDRAM Controller or Static Memory Controller on NCS1
鈥� Static Memory Controller on NCS2
鈥� Static Memory Controller on NCS3, Optional NAND Flash/SmartMediaTM Support
鈥� Static Memory Controller on NCS4 - NCS5, Optional CompactFlashTM Support
10.8.2
Static Memory Controller
6 Chip Selects Available
64-Mbyte Address Space per Chip Select
8-, 16- or 32-bit Data Bus
Word, Halfword, Byte Transfers
Byte Write or Byte Select Lines
Programmable Setup, Pulse And Hold Time for Read Signals per Chip Select
Programmable Setup, Pulse And Hold Time for Write Signals per Chip Select
Programmable Data Float Time per Chip Select
Compliant with LCD Module
External Wait Request
Automatic Switch to Slow Clock Mode
Asynchronous Read in Page Mode Supported: Page Size Ranges from 4 to 32 Bytes
10.8.3
SDRAM Controller
Numerous Configurations Supported
鈥� 2K, 4K, 8K Row Address Memory Parts
鈥� SDRAM with Two or Four Internal Banks
鈥� SDRAM with 16- or 32-bit Data Path
Programming Facilities
鈥� Word, Half-word, Byte Access
鈥� Automatic Page Break When Memory Boundary Has Been Reached
鈥� Multibank Ping-pong Access
鈥� Timing Parameters Specified by Software
鈥� Automatic Refresh Operation, Refresh Rate is Programmable
鐩搁棞PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| ATTINY24A-MU | MCU AVR 2KB FLASH 20MHZ 20QFN |
| ATTINY24A-CCU | MCU AVR 2KB FLASH 20MHZ 15-UFBGA |
| ATTINY13-20MU | IC MCU AVR 1K FLASH 10MHZ 20-MLF |
| ATTINY24A-SSU | MCU AVR 2K FLASH 20MHZ 14SOIC |
| ATTINY13A-MMU | IC MCU AVR 1K FLASH 20MHZ 10-DFN |
鐩搁棞浠ｇ悊鍟�/鎶€琛撳弮鏁�(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| ATTINY24A-SSFR | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 2KB FL 128B EE SRAM USIADC 20MHz Hi+125C RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰ㄦ牸:SMD/SMT |
| ATTINY24A-SSN | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 2K FLASH 128B EE 128B SRAM USI RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰ㄦ牸:SMD/SMT |
| ATTINY24A-SSNR | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU AVR 2KB FL 128B EE USI ADC 20MHz 105C RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰ㄦ牸:SMD/SMT |
| ATTINY24A-SSU | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 20MHz, Ind Temp 1.8-5.5V, Green RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰ㄦ牸:SMD/SMT |
| ATTINY24A-SSUR | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU AVR 2KB FLSH 128B EE USI ADC 20MHz 1.8V RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰ㄦ牸:SMD/SMT |
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