參數(shù)資料
型號(hào)： ATTINY15L-1SI
廠商： Atmel
文件頁(yè)數(shù)： 7/85頁(yè)
文件大?。?/td> 0K
描述： IC AVR MCU 1K FLASH 2.7V SO8
標(biāo)準(zhǔn)包裝： 95
系列： AVR® ATtiny
核心處理器： AVR
芯體尺寸： 8-位
速度： 1.6MHz
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 6
程序存儲(chǔ)器容量： 1KB（512 x 16）
程序存儲(chǔ)器類型： 閃存
EEPROM 大小： 64 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 8-SOIC（0.209"，5.30mm 寬）
包裝： 管件
15
ATtiny15L
1187H–AVR–09/07
Notes:
1. On Power-up, the start-up time is increased with typical 0.6 ms.
2. “0” means programmed, “1” means unprogrammed.
Table 5 shows the start-up times from Reset. When the CPU wakes up from Power-
down, only the clock-counting part of the start-up time is used. The Watchdog Oscillator
is used for timing the real-time part of the start-up time. The number Watchdog Oscilla-
tor cycles used for each time-out is shown in Table 6.
The frequency of the Watchdog Oscillator is voltage dependent as shown in the Electri-
cal Characteristics section on page 64. The device is shipped with CKSEL = “00”.
Power-on Reset
A Power-on Reset (POR) pulse is generated by an On-chip Detection circuit. The detec-
tion level is nominally defined in Table 4. The POR is activated whenever V
CC is below
the detection level. The POR circuit can be used to trigger the Start-up Reset, as well as
detect a failure in supply voltage.
A Power-on Reset (POR) circuit ensures that the device is Reset from Power-on.
Reaching the Power-on Reset threshold voltage invokes a delay counter, which deter-
mines the delay, for which the device is kept in RESET after V
CC rise. The Time-out
period of the delay counter can be defined by the user through the CKSEL Fuses. The
different selections for the delay period are presented in Table 5. The RESET signal is
activated again, without any delay, when the V
CC decreases below detection level.
Table 5. Reset Delay Selections(1)
BODEN(2)
CKSEL [1:0](2)
Start-up Time,
t
TOUT at VCC = 2.7V
Start-up Time,
t
TOUT at VCC = 5.0V
Recommended
Usage
x
00
256 ms + 18 CK
64 ms + 18 CK
BOD disabled,
slowly rising
power
x
01
256 ms + 18 CK
64 ms + 18 CK
BOD disabled,
slowly rising
power
x
10
16 ms + 18 CK
4 ms + 18 CK
BOD disabled,
quickly rising
power
1
11
18 CK + 32 s
18 CK + 8 s
BOD disabled
0
11
18 CK + 128 s
18 CK + 32 s
BOD enabled
Table 6. Number of Watchdog Oscillator Cycles
V
CC Conditions
Time-out
Number of Cycles
2.7V
32 s
8
2.7V
128 s
32
2.7V
16 ms
4K
2.7V
256 ms
64K
5.0V
8 s
8
5.0V
32 s
32
5.0V
4 ms
4K
5.0V
64 ms
64K
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