參數(shù)資料
型號(hào): ATTINY15L-1PC
廠商: Atmel
文件頁(yè)數(shù): 33/85頁(yè)
文件大?。?/td> 0K
描述: IC AVR MCU 1K FLASH 2.7V 8DIP
標(biāo)準(zhǔn)包裝: 50
系列: AVR® ATtiny
核心處理器: AVR
芯體尺寸: 8-位
速度: 1.6MHz
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 6
程序存儲(chǔ)器容量: 1KB(512 x 16)
程序存儲(chǔ)器類型: 閃存
EEPROM 大小: 64 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x10b
振蕩器型: 內(nèi)部
工作溫度: 0°C ~ 70°C
封裝/外殼: 8-DIP(0.300",7.62mm)
包裝: 管件
39
ATtiny15L
1187H–AVR–09/07
The Analog
Comparator
The Analog Comparator compares the input values on the positive pin PB0 (AIN0) and
negative pin PB1 (AIN1). When the voltage on the positive pin PB0 (AIN0) is higher than
the voltage on the negative pin PB1 (AIN1), the Analog Comparator Output (ACO) is set
(one). The comparator’s output can trigger a separate interrupt, exclusive to the Analog
Comparator. The user can select interrupt triggering on comparator output rise, fall or
toggle. A block diagram of the Comparator and its surrounding logic is shown in Figure
Figure 24. Analog Comparator Block Diagram
The Analog Comparator
Control and Status Register –
ACSR
Bit 7 – ACD: Analog Comparator Disable
When this bit is set (one), the power to the Analog Comparator is switched off. This bit
can be set at any time to turn off the Analog Comparator. This will reduce power con-
sumption in Active and Idle mode. When changing the ACD-bit, the Analog Comparator
Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can
occur when the bit is changed.
Bit 6 – ACBG: Analog Comparator Bandgap Select
When this bit is set, a fixed bandgap voltage of 1.22 ± 0.05V replaces the normal input
to the positive pin (AIN0) of the comparator. When this bit is cleared, the normal input
pin PB0 is applied to the positive pin of the comparator.
Bit 5 – ACO: Analog Comparator Output
ACO is directly connected to the comparator output.
Bit 4 – ACI: Analog Comparator Interrupt Flag
This bit is set (one) when a comparator output event triggers the interrupt mode defined
by ACI1 and ACI0. The Analog Comparator Interrupt routine is executed if the ACIE bit
is set (one) and the I-bit in SREG is set (one). ACI is cleared by hardware when execut-
ing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a
logical “1” to the flag.
Bit
7654
321
0
$08
ACD
ACBG
ACO
ACI
ACIE
ACIS1
ACIS0
ACSR
Read/Write
R/W
R
R/W
R
R/W
Initial Value
0
X
0
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