參數(shù)資料
型號: ATTINY12V-1SI
廠商: Atmel
文件頁數(shù): 11/15頁
文件大小: 0K
描述: IC AVR MCU 1MHZ 1.8V SO-8
標準包裝: 95
系列: AVR® ATtiny
核心處理器: AVR
芯體尺寸: 8-位
速度: 1.2MHz
外圍設備: POR,WDT
輸入/輸出數(shù): 6
程序存儲器容量: 1KB(512 x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 64 x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 8-SOIC(0.209",5.30mm 寬)
包裝: 管件
配用: ATAVRISP2-ND - PROGRAMMER AVR IN SYSTEM
其它名稱: ATTINY12V1SI
5
ATtiny11/12
1006FS–AVR–06/07
Pin Descriptions
VCC
Supply voltage pin.
GND
Ground pin.
Port B (PB5..PB0)
Port B is a 6-bit I/O port. PB4..0 are I/O pins that can provide internal pull-ups (selected
for each bit). On ATtiny11, PB5 is input only. On ATtiny12, PB5 is input or open-drain
output. The port pins are tri-stated when a reset condition becomes active, even if the
clock is not running. The use of pins PB5..3 as input or I/O pins is limited, depending on
reset and clock settings, as shown below.
Notes:
1. “Used” means the pin is used for reset or clock purposes.
2. “-” means the pin function is unaffected by the option.
3. Input means the pin is a port input pin.
4. On ATtiny11, PB5 is input only. On ATtiny12, PB5 is input or open-drain output.
5. I/O means the pin is a port input/output pin.
XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier.
RESET
Reset input. An external reset is generated by a low level on the RESET pin. Reset
pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter
pulses are not guaranteed to generate a reset.
Table 2. PB5..PB3 Functionality vs. Device Clocking Options
Device Clocking Option
PB5
PB4
PB3
External Reset Enabled
Used(1)
-
External Reset Disabled
--
External Crystal
-
Used
External Low-frequency Crystal
-
Used
External Ceramic Resonator
-
Used
External RC Oscillator
-
I/O(5)
Used
External Clock
-
I/O
Used
Internal RC Oscillator
-
I/O
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