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參數(shù)資料
| 型號(hào)： | ATT3064-100J68I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | FPGA |
| 英文描述： | Field-Programmable Gate Arrays |
| 中文描述： | 現(xiàn)場(chǎng)可編程門陣列 |
| 文件頁數(shù)： | 18/80頁 |
| 文件大小： | 528K |
| 代理商： | ATT3064-100J68I |
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Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
18
Lucent Technologies Inc.
Configuration
(continued)
Figure 18. State Diagram of Configuration Process for Powerup and Reprogram
5-3110(F)
INITIALIZATION
POWER-ON
TIME DELAY
CLEAR
CONFIGURATION
MEMORY
YES
RESET
ACTIVE
NO
TEST
MODE PINS
CONFIGURATION
PROGRAM MODE
OPERATIONAL
MODE
START-UP
INIT = LOW
USER I/O PINS WITH HIGH-IMPEDANCE PULL-UP
HDC = HIGH
LDC = LOW
ACTIVE RESET
POWERDOWN
NO HDC, LDC
OR PULL-UP
INACTIVE
PWRDWN
ACTIVE RESET
OPERATES ON
USER LOGIC
LOW ON DONE/PROG AND RESET
ACTIVE
PWRDWN
Length count control allows a system of multiple
FPGAs in assorted sizes to begin operation in a syn-
chronized fashion. The configuration program gener-
ated by the
ORCA
Foundry Development System
begins with a preamble of 111111110010 (binary), fol-
lowed by a 24-bit length count representing the total
number of configuration clocks needed to complete
loading of the configuration program(s). The data fram-
ing is shown in Figure 19. All FPGAs connected in
series read and shift preamble and length count in (on
positive) and out (on negative) CCLK edges. An FPGA
which has received the preamble and length count then
presents a HIGH data out until it has intercepted the
appropriate number of data frames. When the configu-
ration program memory of an FPGA is full and the
length count does not compare, the FPGA shifts any
additional data through, as it did for preamble and
length count.
When the FPGA configuration memory is full and the
length count compares, the FPGA will execute a syn-
chronous start-up sequence and become operational
(see Figure 20 on page 20). Two CCLK cycles after the
completion of loading configuration data, the user
I/O pins are enabled as configured. As selected in
ORCA
Foundry, the internal user-logic reset is released
either one clock cycle before or after the I/O pins
become active. A similar timing selection is program-
mable for the DONE/
PROG
output signal. DONE/
PROG
may also be programmed to be an open drain or
include a pull-up resistor to accommodate wired-
ANDing. The high during configuration (HDC) and low
during configuration (
LDC
) are two user I/O pins which
are driven active when an FPGA is in initialization,
clear, or configure states. These signals and DONE/
PROG
provide for control of external logic signals such
as reset, bus enable, or PROM enable during
configuration.
For parallel master configuration modes, these signals
provide PROM enable control and allow the data pins
to be shared with user logic signals.
User I/O inputs can be programmed to be either TTL or
CMOS compatible thresholds. At powerup, all inputs
have TTL thresholds and can change to CMOS thresh-
olds at the completion of configuration, if the user has
selected CMOS thresholds. The threshold of
PWRDWN
and the direct clock inputs are fixed at a CMOS level.
If the crystal oscillator is used, it will begin operation
before configuration is complete to allow time for
stabilization before it is connected to the internal
circuitry.
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