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參數(shù)資料
| 型號(hào)： | ATT3042-125M44I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | FPGA |
| 英文描述： | Field-Programmable Gate Arrays |
| 中文描述： | 現(xiàn)場(chǎng)可編程門陣列 |
| 文件頁數(shù)： | 33/80頁 |
| 文件大?。?/td> | 528K |
| 代理商： | ATT3042-125M44I |
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Lucent Technologies Inc.
33
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Power
(continued)
Power Dissipation
The FPGA exhibits the low power consumption charac-
teristic of CMOS ICs. The configuration option of TTL
chip input threshold requires power for the threshold
reference. The power required by the static memory
cells that hold the configuration data is very low and
may be maintained in a powerdown mode.
Typically, most of the power dissipation is produced by
external capacitive loads on the output buffers. This
load and frequency dependent power is 25 μW/pF/MHz
per output. Another component of I/O power is the dc
loading on each output pin by devices driven by the
FPGA.
Internal power dissipation is a function of the number
and size of the nodes, and the frequency at which they
change. In an FPGA, the fraction of nodes changing on
a given clock is typically low (10% to 20%). For
example, in a large binary counter, the average clock
cycle produces changes equal to one CLB output at
the clock frequency. Typical global clock buffer power is
between 1.7 mW/MHz for the ATT3020 and 3.5 mW/
MHz for the ATT3090. The internal capacitive load is
more a function of interconnect than fan-out. With a
typical load of three general interconnect segments,
each configurable logic block output requires about
0.22 mW/MHz of its output frequency:
Total Power = V
CC
+ I
CCO
+ External
(dc + Capacitive) + Internal
(CLB + IOB + Long Line + Pull-up)
Because the control storage of the FPGA is CMOS
static memory, its cells require a very low standby cur-
rent for data retention. In some systems, this low data
retention current characteristic can be used as a
method of preserving configurations in the event of a
primary power loss. The FPGA has built-in powerdown
logic which, when activated, will disable normal opera-
tion of the device and retain only the configuration data.
All internal operation is suspended and output buffers
are placed in their high-impedance state with no pull-
ups. Powerdown data retention is possible with a sim-
ple battery backup circuit, because the power require-
ment is extremely low. For retention at 2.4 V, the
required current is typically on the order of 50 nA.
To force the FPGA into the powerdown state, the user
must pull the
PWRDWN
pin low and continue to supply
a retention voltage to the V
CC
pins of the package.
When normal power is restored, V
CC
is elevated to its
normal operating voltage and
PWRDWN
is returned to a
high. The FPGA resumes operation with the same
internal sequence that occurs at the conclusion of
configuration. Internal I/O and logic block storage ele-
ments will be reset, the outputs will become enabled,
and the DONE/
PROG
pin will be released. No configu-
ration programming is involved.
When the power supply is removed from a CMOS
device, it is possible to supply some power from an
input signal. The conventional electrostatic input pro-
tection is implemented with diodes to the supply and
ground. A positive voltage applied to an I/O will cause
the positive protection diode to conduct and drive the
power pin. This condition can produce invalid power
conditions and should be avoided. A large series resis-
tor might be used to limit the current or a bipolar buffer
may be used to isolate the input signal.
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