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    參數(shù)資料
    型號: ATT3020-125M68I
    廠商: Electronic Theatre Controls, Inc.
    元件分類: FPGA
    英文描述: Field-Programmable Gate Arrays
    中文描述: 現(xiàn)場可編程門陣列
    文件頁數(shù): 37/80頁
    文件大?。?/td> 528K
    代理商: ATT3020-125M68I
    Data Sheet
    February 1997
    ATT3000 Series Field-Programmable Gate Arrays
    Lucent Technologies Inc.
    37
    Pin Information
    (continued)
    Table 6A. ATT3000 Family Configuration (44, 68, and 84 PLCC; 100 QFP; and 100 TQFP)
    Configuration Mode (M2:M1:M0)
    44
    PLCC
    *
    68
    PLCC
    84
    PLCC
    100
    QFP
    100
    TQFP
    User
    Operation
    Slave
    (1:1:1)
    Master-Serial
    (0:0:0)
    Peripheral
    (1:0:1)
    Master-High
    (1:1:0)
    Master-Low
    (1:0:0)
    PWRDWN
    V
    CC
    M1 (High)
    M0 (High)
    M2 (High)
    HDC (High)
    LDC
    (Low)
    INIT
    GND
    PWRDWN
    V
    CC
    M1 (Low)
    M0 (Low)
    M2 (Low)
    HDC (High)
    LDC
    (Low)
    INIT
    GND
    PWRDWN
    V
    CC
    M1 (Low)
    M0 (Low)
    M2 (High)
    HDC (High)
    LDC
    (Low)
    INIT
    GND
    PWRDWN
    V
    CC
    M1 (High)
    M0 (High)
    M2 (High)
    HDC (High)
    LDC
    (Low)
    INIT
    GND
    PWRDWN
    V
    CC
    M1 (Low)
    M0 (Low)
    M2 (Low)
    HDC (High)
    LDC
    (Low)
    INIT
    GND
    7
    10
    18
    25
    26
    27
    28
    30
    34
    35
    43
    44
    45
    46
    47
    48
    49
    50
    51
    52
    53
    54
    55
    56
    57
    58
    59
    60
    61
    62
    63
    64
    65
    66
    67
    68
    1
    2
    3
    4
    5
    6
    7
    8
    9
    12
    22
    31
    32
    33
    34
    36
    42
    43
    53
    54
    55
    56
    57
    58
    60
    61
    62
    64
    65
    66
    67
    70
    71
    72
    73
    74
    75
    76
    77
    78
    81
    82
    83
    84
    1
    2
    3
    4
    5
    8
    9
    10
    11
    29
    41
    52
    54
    56
    57
    59
    65
    66
    76
    78
    80
    81
    82
    83
    87
    88
    89
    91
    92
    93
    94
    98
    99
    100
    1
    2
    5
    6
    8
    9
    12
    13
    14
    15
    16
    17
    18
    19
    20
    23
    24
    25
    26
    26
    38
    49
    51
    53
    54
    56
    62
    63
    73
    75
    77
    78
    79
    80
    84
    85
    86
    88
    89
    90
    91
    95
    96
    97
    98
    99
    2
    3
    5
    6
    9
    10
    11
    12
    13
    14
    15
    16
    17
    20
    21
    22
    23
    PWRDWN
    V
    CC
    RDATA
    RTRIG
    I/O
    I/O
    I/O
    I/O
    GND
    XTL2–I/O
    RESET
    PROG
    I/O
    XTL1–I/O
    I/O
    I/O
    I/O
    I/O
    V
    CC
    I/O
    I/O
    I/O
    I/O
    I/O
    I/O
    I/O
    CCLK
    I/O
    I/O
    I/O
    I/O
    I/O
    I/O
    I/O
    I/O
    GND
    I/O
    I/O
    I/O
    I/O
    I/O
    I/O
    I/O
    I/O
    12
    16
    17
    18
    19
    20
    22
    23
    26
    27
    28
    30
    34
    38
    39
    40
    1
    RESET
    DONE
    RESET
    DONE
    RESET
    DONE
    D7
    RESET
    DONE
    D7
    RESET
    DONE
    D7
    D6
    D5
    CS0
    D4
    V
    CC
    D3
    CS1
    D2
    D1
    D6
    D5
    D4
    V
    CC
    D3
    D2
    D1
    RCLK
    D0
    DOUT
    CCLK
    A0
    A1
    A2
    A3
    A15
    A4
    A14
    A5
    GND
    A13
    A6
    A12
    A7
    A11
    A8
    A10
    A9
    D6
    D5
    D4
    V
    CC
    D3
    D2
    D1
    RCLK
    D0
    DOUT
    CCLK
    A0
    A1
    A2
    A3
    A15
    A4
    A14
    A5
    GND
    A13
    A6
    A12
    A7
    A11
    A8
    A10
    A9
    V
    CC
    V
    CC
    RDY/
    BUSY
    D0
    DOUT
    CCLK
    WS
    CS2
    DIN
    DOUT
    CCLK
    DIN
    DOUT
    CCLK
    GND
    GND
    GND
    *
    INIT
    is an open-drain output during configuration.
    Represents a 50 k
    to 100 k
    pull-up.
    Peripheral mode and master parallel mode are not supported in the 44-pin PLCC package; see Table 7.
    Pin assignments for the ATT3064/ATT3090 differ from those shown; see page 42.
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