參數(shù)資料
型號: ATSAM3SD8CA-AU
廠商: Atmel
文件頁數(shù): 16/57頁
文件大?。?/td> 0K
描述: IC MCU 2X256KB CORTEX-M3 100LQFP
標(biāo)準(zhǔn)包裝: 90
系列: SAM3S
核心處理器: ARM? Cortex?-M3
芯體尺寸: 32-位
速度: 64MHz
連通性: EBI/EMI,I²C,IrDA,MMC,SPI,SSC,UART/USART,USB
外圍設(shè)備: 欠壓檢測/復(fù)位,DMA,I²S,POR,PWM,WDT
輸入/輸出數(shù): 79
程序存儲器容量: 512KB(512K x 8)
程序存儲器類型: 閃存
RAM 容量: 64K x 8
電壓 - 電源 (Vcc/Vdd): 1.62 V ~ 1.95 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x12b,D/A 2x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-LQFP
包裝: 托盤
23
11090BS–ATARM–22-Oct-13
SAM3S8/SD8 Summary
6.3
Test Pin
The TST pin is used for JTAG Boundary Scan Manufacturing Test or Fast Flash programming
mode of the SAM3S8/SD8 series. The TST pin integrates a permanent pull-down resistor of
about 15 k
Ω to GND, so that it can be left unconnected for normal operations. To enter fast pro-
gramming mode, see the Fast Flash Programming Interface (FFPI) section. For more on the
manufacturing and test mode, refer to the “Debug and Test” section of the product datasheet.
6.4
NRST Pin
The NRST pin is bidirectional. It is handled by the on-chip reset controller and can be driven low
to provide a reset signal to the external components or asserted low externally to reset the
microcontroller. It will reset the Core and the peripherals except the Backup region (RTC, RTT
and Supply Controller). There is no constraint on the length of the reset pulse and the reset con-
troller can guarantee a minimum pulse length. The NRST pin integrates a permanent pull-up
resistor to VDDIO of about 100 k
Ω. By default, the NRST pin is configured as an input.
6.5
ERASE Pin
The ERASE pin is used to reinitialize the Flash content (and some of its NVM bits) to an erased
state (all bits read as logic level 1). It integrates a pull-down resistor of about 100 k
Ω to GND, so
that it can be left unconnected for normal operations.
This pin is debounced by SCLK to improve the glitch tolerance. When the ERASE pin is tied high
during less than 100 ms, it is not taken into account. The pin must be tied high during more than
220 ms to perform a Flash erase operation.
The ERASE pin is a system I/O pin and can be used as a standard I/O. At startup, the ERASE
pin is not configured as a PIO pin. If the ERASE pin is used as a standard I/O, startup level of
this pin must be low to prevent unwanted erasing. Refer to Section 10.17 “Peripheral Signal Mul-
tiplexing on I/O Lines” on page 40. Also, if the ERASE pin is used as a standard I/O output,
asserting the pin to low does not erase the Flash.
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