參數(shù)資料
型號: ATSAM3N1BB-MU
廠商: Atmel
文件頁數(shù): 33/60頁
文件大?。?/td> 0K
描述: IC MCU 64KB CORTEX-M3 64-QFN
標(biāo)準(zhǔn)包裝: 260
系列: SAM3N
核心處理器: ARM? Cortex?-M3
芯體尺寸: 32-位
速度: 48MHz
連通性: I²C,IrDA,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,DMA,POR,PWM,WDT
輸入/輸出數(shù): 47
程序存儲器容量: 64KB(64K x 8)
程序存儲器類型: 閃存
RAM 容量: 8K x 8
電壓 - 電源 (Vcc/Vdd): 1.62 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 10x10b,D/A 1x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-VFQFN 裸露焊盤
包裝: 托盤
39
11011BS–ATARM–22-Feb-12
SAM3N Summary
10.8
SysTick Timer
24-bit down counter
Self-reload capability
Flexible System timer
10.9
Real-time Timer
Real-time Timer, allowing backup of time with different accuracies
– 32-bit Free-running back-up Counter
– Integrates a 16-bit programmable prescaler running on slow clock
– Alarm register capable to generate a wake-up of the system through the Shut Down
Controller
10.10 Real Time Clock
Low power consumption
Full asynchronous design
Two hundred year calendar
Programmable Periodic Interrupt
Alarm and update parallel load
Control of alarm and update Time/Calendar Data In
10.11 General Purpose Backup Registers
Eight 32-bit general-purpose backup registers
10.12 Nested Vectored Interrupt Controller
Thirty Two maskable external interrupts
Sixteen priority levels
Processor state automatically saved on interrupt entry, and restored on
Dynamic reprioritization of interrupts
Priority grouping
– selection of pre-empting interrupt levels and non pre-empting interrupt levels
Support for tail-chaining and late arrival of interrupts
– back-to-back interrupt processing without the overhead of state saving and
restoration between interrupts.
Processor state automatically saved on interrupt entry and restored on interrupt exit, with no
instruction overhead
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