- 您現(xiàn)在的位置：買賣IC網(wǎng) > Datasheet目錄60 > ATS682LSHTN-T (Allegro Microsystems Inc)IC HALL EFFECT SENSOR 4SIP Datasheet資料下載
參數(shù)資料
| 型號： | ATS682LSHTN-T |
| 廠商： | Allegro Microsystems Inc |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 317K |
| 描述： | IC HALL EFFECT SENSOR 4SIP |
| 產(chǎn)品培訓(xùn)模塊： | Current Sensor |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 傳感范圍： | 120mV 跳閘，120mV 釋放 |
| 類型： | 線性場傳感器 |
| 電源電壓： | 4 V ~ 24 V |
| 電流 - 電源： | 16.8mA |
| 輸出類型： | 模擬 |
| 特點： | 輪齒類型 |
| 工作溫度： | -40°C ~ 150°C |
| 封裝/外殼： | 4-SIP |
| 供應(yīng)商設(shè)備封裝： | 4-SIP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁面： | 1142 (CN2011-ZH PDF) |
| 其它名稱： | 620-1327-6 |
Miniature, Two-Wire, True Zero Speed
Differential Peak-Detecting Sensor IC
ATS682LSH
12
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Device Operation
Power-On When power (V
CC
> V
CC
(min)) is applied to the
device, a short period of time is required to activate the various
portions of the IC. During this period, the ATS682 powers-on in
the high current state, I
CC(HIGH)
. After power-on, there are condi-
tions that could induce a change in the output state. Such an event
could be caused by thermal transients, but it would also require a
static applied magnetic field, proper signal polarity, and particular
direction and magnitude of internal signal drift.
Initial Offset Adjust The IC initially compensates for differ-
ential offset, 擝
APP
, that results from chip, magnet, and instal-
lation alignment. Once the effective differential magnetic offset
has been cancelled, the digital tracking DAC is ready to track the
signal and provide output switching.
The period of time required for both power-on and initial offset
adjust is defined as the Power-On Time specification.
Calibration Mode The calibration mode allows the IC to auto-
matically select the proper signal gain and continue to adjust for
DC differential magnetic offset. The AGC is active, and selects
the optimal signal gain based on the amplitude of the V
PROC
signal. Following each adjustment to the AGC DAC, the Offset
DAC is also adjusted to ensure the internal analog signal is prop-
erly centered. During this mode, the tracking DAC is active and
output switching occurs, but the duty cycle is not guaranteed to
be within specification.
Running Mode After the initial calibration process (CAL
I
edges) establishes a signal gain, the device moves to Running
mode. During Running mode, the IC tracks the input signal and
continues to give an output edge for every peak of the signal.
AOA remains active to compensate for any offset drift over time.
The ATS682 also incorporates an algorithm for adjusting the
signal gain during Running mode. This algorithm is designed to
optimize the V
PROC
signal amplitude in instances where the mag-
netic signal during the calibration period is not representative of
the amplitude of the magnetic signal for the installed application
air gap (see figure 9).
IC Electrical
Output, I
OUT
Internal Differential
Signal, V
PROC
BRP
B
OP
BOP
B
RP
1
2
3
4
5
Figure 9: Operation of Running Mode Gain Adjust.
Position 1. The device is initially powered-on. Self-calibration occurs.
Position 2. Small amplitude oscillation of the target sends an erroneously small differential signal to the device. The amplitude of V
PROC
is greater than
the switching hysteresis (B
OP
and B
RP
), and the device output switches.
Position 3. The calibration period completes on the third rising output edge, and the device enters Running mode.
Position 4. True target rotation occurs and the correct magnetic signal is generated for the installation air gap. The established signal gain is too large for
the rotational magnetic signal of the target, at the given air gap.
Position 5. Running mode calibration corrects the signal gain to an optimal level for the installation air gap.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ATS685LSHTN-T | IC HALL EFFECT GEAR SENSOR 4SIP |
| BU52001GUL-E2 | IC HALL EFFECT SW BIPO VCSP50L1 |
| BU52003GUL-E2 | IC HALL EFFECT SW BIPO VCSP50L1 |
| BU52014HFV-TR | IC HALL EFFECT SW BIPO HVSOF5 |
| BU52040HFV-TR | IC HALL EFFECT BIPO LATCH HVSOF5 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ATS684LSNTN-T | 功能描述:TWO-WIRE DIFF SPEED SENSOR IC WI 制造商:allegro microsystems, llc 系列:- 包裝:剪切帶（CT） 零件狀態(tài):在售 功能:專用型 技術(shù):霍爾效應(yīng) 極化:單向 感應(yīng)范圍:70% 跳閘，30% 釋放 測試條件:25°C 電壓 - 電源:4 V ~ 24 V 電流 - 電源（最大值）:16mA 電流 - 輸出（最大值）:- 輸出類型:電流源 特性:- 工作溫度:-40°C ~ 150°C 封裝/外殼:3-SIP 供應(yīng)商器件封裝:3-SIP 標(biāo)準(zhǔn)包裝:1 |
| ATS685LSH | 制造商:ALLEGRO 制造商全稱:Allegro MicroSystems 功能描述:Two-Wire, Zero Speed Differential Gear Tooth Sensor IC |
| ATS685LSHTN-T | 功能描述:IC HALL EFFECT GEAR SENSOR 4SIP RoHS:是 類別:傳感器，轉(zhuǎn)換器 >> 磁性 - 霍爾效應(yīng)，數(shù)字式開關(guān)，線性，羅盤 (IC) 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 傳感范圍:20mT ~ 80mT 類型:旋轉(zhuǎn) 電源電壓:4.5 V ~ 5.5 V 電流 - 電源:15mA 電流 - 輸出（最大）:- 輸出類型:數(shù)字式，PWM，8.5 位串行 特點:可編程 工作溫度:-40°C ~ 150°C 封裝/外殼:20-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:20-SSOP 包裝:Digi-Reel® 其它名稱:AS5132-HSST-500DKR |
| ATS692LSHTN-RSNPH-T | 功能描述:IC HALL EFFECT SENSOR 4SIP 制造商:allegro microsystems, llc 系列:- 包裝:帶卷（TR） 零件狀態(tài):有效 功能:專用型 技術(shù):霍爾效應(yīng) 極化:- 感應(yīng)范圍:69% 跳閘，31% 釋放 測試條件:-40°C ~ 150°C 電壓 - 電源:4 V ~ 24 V 電流 - 電源（最大值）:16.5mA 電流 - 輸出（最大值）:- 輸出類型:電流 特性:- 工作溫度:-40°C ~ 150°C（TA） 封裝/外殼:4-SIP 模塊 供應(yīng)商器件封裝:4-SIP 標(biāo)準(zhǔn)包裝:800 |
| ATS693LSGTN-RSNYPH-T | 功能描述:IC HALL EFFECT SENSOR 4SIP 制造商:allegro microsystems, llc 系列:- 包裝:帶卷（TR） 零件狀態(tài):有效 功能:專用型 技術(shù):霍爾效應(yīng) 極化:- 感應(yīng)范圍:69% 跳閘，31% 釋放 測試條件:-40°C ~ 150°C 電壓 - 電源:4 V ~ 24 V 電流 - 電源（最大值）:16.5mA 電流 - 輸出（最大值）:- 輸出類型:電流 特性:- 工作溫度:-40°C ~ 150°C（TA） 封裝/外殼:4-SIP 模塊 供應(yīng)商器件封裝:4-SIP 標(biāo)準(zhǔn)包裝:800 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。