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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� ATMEGA8U2-MUR
寤犲晢锛� Atmel
鏂囦欢闋佹暩(sh霉)锛� 302/310闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� MCU AVR 8K FLASH 16MHZ 32VQFN
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� MCU Product Line Introduction
megaAVR Introduction
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 5,000
绯诲垪锛� AVR® ATmega
鏍稿績铏曠悊鍣細 AVR
鑺珨灏哄锛� 8-浣�
閫熷害锛� 16MHz
閫i€氭€э細 SPI锛孶ART/USART锛孶SB
澶栧湇瑷�(sh猫)鍌欙細 娆犲妾㈡脯/寰�(f霉)浣�锛孭OR锛孭WM锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 22
绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲忥細 8KB锛�4K x 16锛�
绋嬪簭瀛樺劜(ch菙)鍣ㄩ鍨嬶細 闁冨瓨
EEPROM 澶�?銆�?/td> 512 x 8
RAM 瀹归噺锛� 512 x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 2.7 V ~ 5.5 V
鎸暕鍣ㄥ瀷锛� 鍏�(n猫i)閮�
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 32-VFQFN 瑁搁湶鐒婄洡
鍖呰锛� 甯跺嵎 (TR)
鍏跺畠鍚嶇ū锛� ATMEGA8U2-MUR-ND
ATMEGA8U2-MURTR
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91
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ATmega8U2/16U2/32U2
15. 8-bit Timer/Counter0 with PWM
15.1
Features
Two Independent Output Compare Units
Double Buffered Output Compare Registers
Clear Timer on Compare Match (Auto Reload)
Glitch Free, Phase Correct Pulse Width Modulator (PWM)
Variable PWM Period
Frequency Generator
Three Independent Interrupt Sources (TOV0, OCF0A, and OCF0B)
15.2
Overview
Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output
Compare Units, and with PWM support. It allows accurate program execution timing (event man-
agement) and wave generation.
A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 15-1. For the actual
placement of I/O pins, refer to 鈥淧inout鈥� on page 2. CPU accessible I/O Registers, including I/O
bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed
Figure 15-1.
8-bit Timer/Counter Block Diagram
15.2.1
Registers
The Timer/Counter (TCNT0) and Output Compare Registers (OCR0A and OCR0B) are 8-bit
registers. Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the
Timer Interrupt Flag Register (TIFR0). All interrupts are individually masked with the Timer Inter-
rupt Mask Register (TIMSK0). TIFR0 and TIMSK0 are not shown in the figure.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on
the T0 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter
Clock Select
Timer/Counter
DA
T
A
B
U
S
OCRnA
OCRnB
=
TCNTn
Waveform
Generation
Waveform
Generation
OCnA
OCnB
=
Fixed
TOP
Value
Control Logic
= 0
TOP
BOTTOM
Count
Clear
Direction
TOVn
(Int.Req.)
OCnA
(Int.Req.)
OCnB
(Int.Req.)
TCCRnA
TCCRnB
Tn
Edge
Detector
( From Prescaler )
clk
Tn
鐩搁棞(gu膩n)PDF璩囨枡
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鍙冩暩(sh霉)鎻忚堪
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