參數(shù)資料
型號(hào): ATMEGA64RZAV-10AU
廠商: Atmel
文件頁(yè)數(shù): 19/23頁(yè)
文件大小: 0K
描述: MCU ATMEGA644/AT86RF230 44-TQFP
產(chǎn)品培訓(xùn)模塊: MCU Product Line Introduction
megaAVR Introduction
Introduction to ZigBee Low Power Wireless Networks
標(biāo)準(zhǔn)包裝: 1
系列: ATMEGA
頻率: 2.4GHz
調(diào)制或協(xié)議: 802.15.4 Zigbee
功率 - 輸出: 3dBm
靈敏度: -101dBm
電源電壓: 1.8 V ~ 3.6 V
數(shù)據(jù)接口: PCB,表面貼裝
存儲(chǔ)容量: 64kB 閃存,2kB EEPROM,4kB RAM
天線連接器: PCB,表面貼裝
封裝/外殼: 44-TQFP
包裝: 托盤
產(chǎn)品目錄頁(yè)面: 553 (CN2011-ZH PDF)
配用: ATSTK600-TQFP32-ND - STK600 SOCKET/ADAPTER 32-TQFP
ATAVRISP2-ND - PROGRAMMER AVR IN SYSTEM
ATSTK500-ND - PROGRAMMER AVR STARTER KIT
5
2593OS–AVR–02/12
ATmega644
and source capability. As inputs, Port A pins that are externally pulled low will source current if
the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes
active, even if the clock is not running.
Port A also serves the functions of various special features of the ATmega644 as listed on page
73.
2.2.4
Port B (PB7:PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port B also serves the functions of various special features of the ATmega644 as listed on page
75.
2.2.5
Port C (PC7:PC0)
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port C output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port C also serves the functions of the JTAG interface, along with special features of the
ATmega644 as listed on page 78.
2.2.6
Port D (PD7:PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port D output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port D also serves the functions of various special features of the ATmega644 as listed on page
80.
2.2.7
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in ”System and Reset
Characteristics” on page 320. Shorter pulses are not guaranteed to generate a reset.
2.2.8
XTAL1
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
2.2.9
XTAL2
Output from the inverting Oscillator amplifier.
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