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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | ATMEGA48-15MT |
| 寤�(ch菐ng)鍟嗭細 | Atmel |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 111/240闋�(y猫) |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | MCU AVR 4K FLASH 15MHZ 32-QFN |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | megaAVR Introduction |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 1 |
| 绯诲垪锛� | AVR® ATmega |
| 鏍稿績铏曠悊鍣細 | AVR |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 16MHz |
| 閫ｉ€氭€э細 | I²C锛孲PI锛孶ART/USART |
| 澶栧湇瑷�(sh猫)鍌欙細 | 娆犲妾㈡脯(c猫)/寰�(f霉)浣嶏紝POR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 23 |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲忥細 | 4KB锛�2K x 16锛� |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄩ(l猫i)鍨嬶細 | 闁冨瓨 |
| EEPROM 澶�?銆�?/td> | 256 x 8 |
| RAM 瀹归噺锛� | 512 x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 2.7 V ~ 5.5 V |
| 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� | A/D 8x10b |
| 鎸暕鍣ㄥ瀷锛� | 鍏�(n猫i)閮� |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 32-VFQFN 瑁搁湶鐒婄洡(p谩n) |
| 鍖呰锛� | 鍓垏甯� (CT) |
| 鍏跺畠鍚嶇ū(ch膿ng)锛� | ATMEGA48-15MTCT |
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2011 Microchip Technology Inc.
Preliminary
DS41455B-page 199
PIC16LF1902/3
FIGURE 21-3:
POR AND POR REARM WITH SLOW RISING VDD
21.1
DC Characteristics: PIC16LF1902/3-I/E (Industrial, Extended)
PIC16LF1902/3
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40掳C
TA +85掳C for industrial
-40掳C
TA +125掳C for extended
Param.
No.
Sym.
Characteristic
Min.
Typ
Max.
Units
Conditions
Supply Voltage
D001
VDD
1.8
鈥�
3.6
V
FOSC
16 MHz:
D002*
VDR
RAM Data Retention Voltage(1)
1.5
鈥�
V
Device in Sleep mode
D002A*
VPOR*
Power-on Reset Release Voltage
1.54
1.64
1.74
V
D002B*
VPORR*
Power-on Reset Rearm Voltage
鈥�
1.7
鈥�
V
Device in Sleep mode
D003
VADFVR
Fixed Voltage Reference Voltage for
ADC, Initial Accuracy
6
7
8
鈥�
4
6
%1.024V, VDD
1.8V, 85掳C
1.024V, VDD
1.8V, 125掳C
2.048V, VDD
2.5V, 85掳C
2.048V, VDD
2.5V, 125掳C
D003A
VCDAFVR
Fixed Voltage Reference Voltage for
Comparator and DAC, Initial Accu-
racy
7
8
9
鈥�
5
7
%1.024V, VDD
1.8V, 85掳C
1.024V, VDD
1.8V, 125掳C
2.048V, VDD
2.5V, 85掳C
2.048V, VDD
2.5V, 125掳C
D003B
VLCDFVR
Fixed Voltage Reference Voltage for
LCD Bias, Initial Accuracy
9
9.5
鈥�
9
%3.072V, VDD
3.6V, 85掳C
3.072V, VDD
3.6V, 125掳C
D003C* TCVFVR
Temperature Coefficient, Fixed Volt-
age Reference
鈥�
-130
鈥�
ppm/掳C
D003D*
VFVR/
VIN
Line Regulation, Fixed Voltage Ref-
erence
鈥�
0.270
鈥�
%/V
D004*
SVDD
VDD Rise Rate
to ensure internal
Power-on Reset signal
0.05
鈥�
V/ms
for details.
*
These parameters are characterized but not tested.
Data in 鈥淭yp鈥� column is at 3.3V, 25掳C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note
1:
This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
VDD
VPOR
VPORR
VSS
NPOR
TPOR(3)
POR REARM
Note
1:
When NPOR is low, the device is held in Reset.
2:
TPOR 1
s typical.
3:
TVLOW 2.7
s typical.
TVLOW(2)
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