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| 型號： | ATMEGA328P-15MZ |
| 廠商： | Atmel |
| 文件頁數(shù)： | 45/83頁 |
| 文件大?。?/td> | 0K |
| 描述： | MCU AVR 32K FLASH 15MHZ 32-QFN |
| 產(chǎn)品培訓模塊： | megaAVR Introduction |
| 標準包裝： | 1 |
| 系列： | AVR® ATmega |
| 核心處理器： | AVR |
| 芯體尺寸： | 8-位 |
| 速度： | 16MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設備： | 欠壓檢測/復位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 23 |
| 程序存儲器容量： | 32KB（16K x 16） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 1K x 8 |
| RAM 容量： | 2K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉換器： | A/D 8x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 包裝： | 剪切帶 (CT) |
| 其它名稱： | ATMEGA328P-15MZCT |
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PIC12(L)F1822/PIC16(L)F1823
DS41413C-page 208
2010-2012 Microchip Technology Inc.
24.2
Compare Mode
Compare mode makes use of the 16-bit Timer1
resource. The 16-bit value of the CCPR1H:CCPR1L
register pair is constantly compared against the 16-bit
value of the TMR1H:TMR1L register pair. When a
match occurs, one of the following events can occur:
Toggle the CCP1 output
Set the CCP1 output
Clear the CCP1 output
Generate a Special Event Trigger
Generate a Software Interrupt
The action on the pin is based on the value of the
CCP1M<3:0> control bits of the CCP1CON register. At
the same time, the interrupt flag CCP1IF bit is set.
All Compare modes can generate an interrupt.
Figure 24-2 shows a simplified diagram of the
Compare operation.
FIGURE 24-2:
COMPARE MODE
OPERATION BLOCK
DIAGRAM
24.2.1
CCP1 PIN CONFIGURATION
The user must configure the CCP1 pin as an output by
clearing the associated TRIS bit.
Also, the CCP1 pin function may be moved to
alternative pins using the APFCON register. Refer to
for more
details.
24.2.2
TIMER1 MODE RESOURCE
In Compare mode, Timer1 must be running in either
Timer mode or Synchronized Counter mode. The
compare operation may not work in Asynchronous
Counter mode.
for more information on configuring Timer1.
24.2.3
SOFTWARE INTERRUPT MODE
When Generate Software Interrupt mode is chosen
(CCP1M<3:0> = 1010), the CCP1 module does not
assert control of the CCP1 pin (see the CCP1CON
register).
24.2.4
SPECIAL EVENT TRIGGER
When Special Event Trigger mode is chosen
(CCP1M<3:0> = 1011), the CCP1 module does the
following:
Resets Timer1
Starts an ADC conversion if ADC is enabled
The CCP1 module does not assert control of the CCP1
pin in this mode.
The Special Event Trigger output of the CCP1 occurs
immediately upon a match between the TMR1H,
TMR1L register pair and the CCPR1H, CCPR1L regis-
ter pair. The TMR1H, TMR1L register pair is not reset
until the next rising edge of the Timer1 clock. The Spe-
cial Event Trigger output starts an A/D conversion (if
the A/D module is enabled). This allows the CCPR1H,
CCPR1L register pair to effectively provide a 16-bit pro-
grammable period register for Timer1.
for more information.
Note:
Clearing the CCP1CON register will force
the CCP1 compare output latch to the
default low level. This is not the PORT I/O
data latch.
CCPR1H CCPR1L
TMR1H
TMR1L
Comparator
QS
R
Output
Logic
Special Event Trigger
Set CCP1IF Interrupt Flag
(PIR1)
Match
TRIS
CCP1M<3:0>
Mode Select
Output Enable
Pin
CCP1
4
Note:
Clocking Timer1 from the system clock
(FOSC) should not be used in Compare
mode. In order for Compare mode to
recognize the trigger event on the CCP1
pin, TImer1 must be clocked from the
instruction clock (FOSC/4) or from an
external clock source.
TABLE 24-3:
SPECIAL EVENT TRIGGER
Device
CCP1/ECCP1
PIC12(L)F1822/16(L)F1823
CCP1
Note 1:
The Special Event Trigger from the CCP
module does not set interrupt flag bit
TMR1IF of the PIR1 register.
2:
Removing the match condition by
changing the contents of the CCPR1H
and CCPR1L register pair, between the
clock edge that generates the Special
Event Trigger and the clock edge that
generates
the
Timer1
Reset,
will
preclude the Reset from occurring.
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