Updated and changed “On-chip Debug System” to
參數(shù)資料
型號: ATMEGA32-16AQ
廠商: Atmel
文件頁數(shù): 11/21頁
文件大?。?/td> 0K
描述: MCU AVR 32K FLASH 16MHZ 44-TQFP
產(chǎn)品培訓(xùn)模塊: MCU Product Line Introduction
megaAVR Introduction
標(biāo)準(zhǔn)包裝: 160
系列: AVR® ATmega
核心處理器: AVR
芯體尺寸: 8-位
速度: 16MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 32KB(16K x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-TQFP
包裝: 托盤
配用: ATSTK524-ND - KIT STARTER ATMEGA32M1/MEGA32C1
ATSTK600-ND - DEV KIT FOR AVR/AVR32
ATAVRDRAGON-ND - KIT DRAGON FLASH MEM AVR
ATSTK500-ND - PROGRAMMER AVR STARTER KIT
19
2503QS–AVR–02/11
ATmega32(L)
Changes from Rev.
2503D-02/03 to
Rev. 2503E-09/03
1.
Updated and changed “On-chip Debug System” to “JTAG Interface and On-chip
Debug System” on page 35.
2.
Updated Table 15 on page 37.
3.
Updated “Test Access Port – TAP” on page 219 regarding the JTAGEN fuse.
4.
Updated description for Bit 7 – JTD: JTAG Interface Disable on page 228.
5.
Added a note regarding JTAGEN fuse to Table 104 on page 257.
6.
Updated Absolute Maximum Ratings* , DC Characteristics and ADC Characteristics in
“Electrical Characteristics” on page 287.
7.
Added a proposal for solving problems regarding the JTAG instruction
IDCODE in
“Errata” on page 336
.
Changes from Rev.
2503C-10/02 to
Rev. 2503D-02/03
1.
Added EEAR9 in EEARH in “Register Summary” on page 327.
2.
Added Chip Erase as a first step in“Programming the Flash” on page 284 and “Pro-
gramming the EEPROM” on page 285.
3.
Removed reference to “Multi-purpose Oscillator” application note and “32 kHz Crys-
tal Oscillator” application note, which do not exist.
4.
Added information about PWM symmetry for Timer0 and Timer2.
5.
Added note in “Filling the Temporary Buffer (Page Loading)” on page 251 about writ-
ing to the EEPROM during an SPM Page Load.
6.
Added “Power Consumption” data in “Features” on page 1.
7.
Added section “EEPROM Write During Power-down Sleep Mode” on page 22.
8.
Added note about Differential Mode with Auto Triggering in “Prescaling and Conver-
sion Timing” on page 204.
9.
Updated Table 89 on page 232.
10.Added updated “Packaging Information” on page 333.
Changes from Rev.
2503B-10/02 to
Rev. 2503C-10/02
1.
Updated the “DC Characteristics” on page 287.
Changes from Rev.
2503A-03/02 to
Rev. 2503B-10/02
1.
Canged the endurance on the Flash to 10,000 Write/Erase Cycles.
2.
Bit nr.4 – ADHSM – in SFIOR Register removed.
3.
Added the section “Default Clock Source” on page 25.
4.
When using External Clock there are some limitations regards to change of fre-
quency. This is described in “External Clock” on page 31 and Table 117 on page 289.
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