80h(2) INDF Addressing " />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� ATMEGA16-16MQR
寤犲晢锛� Atmel
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 113/284闋�(y猫)
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� MCU AVR 16KB FLASH 16MHZ 44QFN
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� megaAVR Introduction
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 1
绯诲垪锛� AVR® ATmega
鏍稿績铏曠悊鍣細 AVR
鑺珨灏哄锛� 8-浣�
閫熷害锛� 16MHz
閫ｉ€氭€э細 I²C锛孲PI锛孶ART/USART
澶栧湇瑷�(sh猫)鍌欙細 娆犲妾㈡脯(c猫)/寰�(f霉)浣�锛孭OR锛孭WM锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 32
绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲忥細 16KB锛�8K x 16锛�
绋嬪簭瀛樺劜(ch菙)鍣ㄩ(l猫i)鍨嬶細 闁冨瓨
EEPROM 澶у皬锛� 512 x 8
RAM 瀹归噺锛� 1K x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 4.5 V ~ 5.5 V
鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� A/D 8x10b
鎸暕鍣ㄥ瀷锛� 鍏�(n猫i)閮�
宸ヤ綔婧害锛� -40°C ~ 105°C
灏佽/澶栨锛� 44-VFQFN 瑁搁湶鐒婄洡(p谩n)
鍖呰锛� 鍓垏甯� (CT)
鍏跺畠鍚嶇ū(ch膿ng)锛� ATMEGA16-16MQRCT
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PIC16(L)F722A/723A
DS41417B-page 20
2010-2012 Microchip Technology Inc.
Bank 1
80h(2)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
xxxx xxxx
81h
OPTION_REG
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
82h(2)
PCL
Program Counter (PC) Least Significant Byte
0000 0000
83h(2)
STATUS
IRP
RP1
RP0
TO
PD
ZDC
C
0001 1xxx
84h(2)
FSR
Indirect Data Memory Address Pointer
xxxx xxxx
85h
TRISA
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
1111 1111
86h
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
1111 1111
87h
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
1111 1111
89h
TRISE
鈥�
TRISE3(5)
鈥�
---- 1111
8Ah(1, 2)
PCLATH
鈥�
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
8Bh(2)
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
8Ch
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
8Dh
PIE2
鈥�
CCP2IE
---- ---0
8Eh
PCON
鈥�
鈥擯OR
BOR
---- --qq
8Fh
T1GCON
TMR1GE
T1GPOL
T1GTM
T1GSPM
T1GGO
DONE
T1GVAL
T1GSS1
T1GSS0
0000 0x00
90h
OSCCON
鈥�
IRCF1
IRCF0
ICSL
ICSS
鈥�
--10 qq--
91h
OSCTUNE
鈥�
TUN5
TUN4
TUN3
TUN2
TUN1
TUN0
--00 0000
92h
PR2
Timer2 Period Register
1111 1111
93h
SSPADD(4)
Synchronous Serial Port (I2C
mode) Address Register
0000 0000
93h
SSPMSK(3)
Synchronous Serial Port (I2C
mode) Address Mask Register
1111 1111
94h
SSPSTAT
SMP
CKE
D/A
PS
R/W
UA
BF
0000 0000
95h
WPUB
WPUB7
WPUB6
WPUB5
WPUB4
WPUB3
WPUB2
WPUB1
WPUB0
1111 1111
96h
IOCB
IOCB7
IOCB6
IOCB5
IOCB4
IOCB3
IOCB2
IOCB1
IOCB0
0000 0000
97h
鈥�
Unimplemented
鈥�
98h
TXSTA
CSRC
TX9
TXEN
SYNC
鈥�
BRGH
TRMT
TX9D
0000 -010
99h
SPBRG
BRG7
BRG6
BRG5
BRG4
BRG3
BRG2
BRG1
BRG0
0000 0000
9Ah
鈥�
Unimplemented
鈥�
9Bh
鈥�
Unimplemented
鈥�
9Ch
APFCON
鈥�
SSSEL
CCP2SEL ---- --00
9Dh
FVRCON
FVRRDY
FVREN
鈥�
ADFVR1
ADFVR0
q0-- --00
9Eh
鈥�
Unimplemented
鈥�
9Fh
ADCON1
鈥�
ADCS2
ADCS1
ADCS0
鈥�
ADREF1
ADREF0
0000 --00
TABLE 2-1:
PIC16(L)F722A/723A SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Page
Legend:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as 鈥�0鈥�, r = reserved.
Shaded locations are unimplemented, read as 鈥�0鈥�.
Note
1:
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are
transferred to the upper byte of the program counter.
2:
These registers can be addressed from any bank.
3:
Accessible only when SSPM<3:0> = 1001.
4:
Accessible only when SSPM<3:0>
1001.
5:
This bit is always 鈥�1鈥� as RE3 is input only.
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
VE-BNP-IY CONVERTER MOD DC/DC 13.8V 50W
VE-B7N-IW-F4 CONVERTER MOD DC/DC 18.5V 100W
VE-BNK-IY CONVERTER MOD DC/DC 40V 50W
VE-B7N-IW-F3 CONVERTER MOD DC/DC 18.5V 100W
VE-B7N-IW-F2 CONVERTER MOD DC/DC 18.5V 100W
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
ATmega16-16MU 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU AVR 16K FLASH 1K SRAM 512B EE RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔(xi脿n)瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT
ATMEGA16-16MUR 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU AVR 128KB FLASH 4KB EE 4KB SRAM RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔(xi脿n)瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT
ATmega16-16PC 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU AVR 16K FLASH 1K SRAM 512B EE RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔(xi脿n)瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT
ATMEGA16-16PI 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU AVR 16K FLASH 1K SRAM 512B EE RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔(xi脿n)瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT
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娣诲姞鏇村閲囪臣(g貌u)

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