參數(shù)資料
型號(hào): ATLV15
廠商: Atmel Corp.
英文描述: ATLV Series Ultra Low Voltage Gate Arrays
中文描述: ATLV系列超低電壓門陣列
文件頁數(shù): 1/7頁
文件大小: 195K
代理商: ATLV15
ATLV
1
ATLV Series
Ultra Low
Voltage
Gate Arrays
Features
Specifically Designed for Battery Powered Applications
1.0 - 3.0 Volts and will Operate from 0.7 to 5.5 Volts
Static Current Drain of <75 nA at 1.0 Volts
200 MHz Maximum Toggle Frequency for Flip Flop at 1.5 Volts
1.0
μ
Drawn Gate Length CMOS Gate Arrays
All Package Styles Offered Including TQFP and TAB
Improved Product Testability Using Serial Scan, Boundary Scan,
and JTAG
Second Source Existing ASIC Design in Atmel's ATLV via Design
Translation. Improved Performance and Lower Cost
ATLV Array Organization
Device
Number
Raw
Gates
Routable
Gates
Max Pin
Count
Max I/O
(1)
Pins
Gate
(2)
Speed
ATLV2
2,000
1,400
44
36
1.3 ns
ATLV3
3,000
1,600
68
60
1.3 ns
ATLV5
5,000
2,800
84
76
1.3 ns
ATLV7
7,000
4,400
100
92
1.3 ns
ATLV10
10,000
6,600
120
112
1.3 ns
ATLV15
15,000
8,000
144
136
1.3 ns
ATLV20
22,000
12,000
160
152
1.3 ns
ATLV35
35,000
18,000
208
192
1.3 ns
Notes: 1. Absolute maximum I/O pins is maximum pin count minus 8. Additional power
and ground pins are assumed to be required to support simultaneous
switching outputs as pin count increases.
2. Nominal 2 input nand gate with a fan out of 2 at 1.5 volts, room temperature.
ATLV2
ATLV3
ATLV5
ATLV7
ATLV10
ATLV15
ATLV20
ATLV35
Description
The ATLV Series CMOS gate arrays employ 1.0
μ
-drawn, double-level metal,
Si-gate, CMOS technology processed in Atmel's U.S.-based, advanced
manufacturing facility. The arrays utilize an enhanced channelless architecture
which results in greater than 50 percent usable gates.
Atmel's flexible design system uses industry design standards and is compatible
with popular CAD/CAE software and hardware packages. The customer can
start designing with the ATLV series today using existing CAD/CAE tools.
0261B
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