參數(shù)資料
型號: ATF750LVC-15XU
廠商: Atmel
文件頁數(shù): 12/19頁
文件大?。?/td> 0K
描述: IC CPLD 15NS 24TSSOP
標準包裝: 62
系列: ATF750LVC
可編程類型: 系統(tǒng)內(nèi)可編程(最少 1K 次編程/擦除循環(huán))
最大延遲時間 tpd(1): 15.0ns
電壓電源 - 內(nèi)部: 3 V ~ 5.5 V
宏單元數(shù): 10
輸入/輸出數(shù): 10
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 24-TSSOP
包裝: 管件
2
1447F–PLD–11/08
ATF750LVC
3.
Pin Configurations
Each of the ATF750LVC’s 22 logic pins can be used as an input. Ten of these can be used as
inputs, outputs or bi-directional I/O pins. Each flip-flop is individually configurable as either
D- or T-type. Each flip-flop output is fed back into the array independently. This allows burying
of all the sum terms and flip-flops.
There are 171 total product terms available. There are two sum terms per output, providing
added flexibility. A variable format is used to assign between four to eight product terms per
sum term. Much more logic can be replaced by this device than by any other 24-pin PLD. With
20 sum terms and flip-flops, complex state machines are easily implemented with logic to
spare.
Product terms provide individual clocks and asynchronous resets for each flip-flop. Each flip-
flop may also be individually configured to have direct input pin controlled clocking. Each out-
put has its own enable product term. One product term provides a common synchronous
preset for all flip-flops. Register preload functions are provided to simplify testing. All registers
automatically reset upon power-up.
Pin Name
Function
CLK
Clock
IN
Logic Inputs
I/O
Bi-directional Buffers
GND
Ground
VCC
3V to 5.5V Supply
3.1
PLCC
Note:
1. For PLCC, pins 1, 8, 15, and 22 can
be left unconnected. For superior
performance, connect VCC to pin 1
and GND to pins 8, 15, and 22.
3.2
DIP/SOIC/TSSOP
5
6
7
8
9
10
11
25
24
23
22
21
20
19
IN
GND(1)
IN
I/O
GND(1)
I/O
4
3
2
1
2
8
27
26
12
1
3
14
15
16
17
1
8
IN
GND
(1)
IN
I/O
IN
CLK/IN
VCC
(1)
VCC
I/O
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CLK/IN
IN
GND
VCC
I/O
IN
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