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參數(shù)資料
| 型號(hào)： | ATF750LVC-15PI |
| 廠商： | Atmel |
| 文件頁數(shù)： | 2/19頁 |
| 文件大小： | 0K |
| 描述： | IC CPLD 15NS LOW VOLT 24-DIP |
| 標(biāo)準(zhǔn)包裝： | 15 |
| 系列： | ATF750LVC |
| 可編程類型： | 系統(tǒng)內(nèi)可編程（最少 1K 次編程/擦除循環(huán)） |
| 最大延遲時(shí)間 tpd(1)： | 15.0ns |
| 電壓電源 - 內(nèi)部： | 3 V ~ 5.5 V |
| 宏單元數(shù)： | 10 |
| 輸入/輸出數(shù)： | 10 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 24-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 24-PDIP |
| 包裝： | 管件 |
| 其它名稱： | ATF750LVC15PI |
10
1447F–PLD–11/08
ATF750LVC
20. Using the ATF750LVC’s Many Advanced Features
The ATF750LVC’s advanced flexibility packs more usable gates into 24-pins than any other
logic device. The ATF750LVCs start with the popular 22V10 architecture, and add several
enhanced features:
Selectable D- and T-type Registers
Each ATF750LVC flip-flop can be individually configured as either D- or T-type. Using the
T-type configuration, JK and SR flip-flops are also easily created. These options allow more
efficient product term usage.
Selectable Asynchronous Clocks
Each of the ATF750LVC’s flip-flops may be clocked by its own clock product term or
directly from Pin 1 (SMD Lead 2). This removes the constraint that all registers must use
the same clock. Buried state machines, counters and registers can all coexist in one device
while running on separate clocks. Individual flip-flop clock source selection further allows
mixing higher performance pin clocking and flexible product term clocking within one
design.
A Full Bank of Ten More Registers
The ATF750LVC provides two flip-flops per output logic cell for a total of 20. Each register
has its own sum term, its own reset term and its own clock term.
Independent I/O Pin and Feedback Paths
Each I/O pin on the ATF750LVC has a dedicated input path. Each of the 20 registers has
its own feedback terms into the array as well. This feature, combined with individual
product terms for each I/O’s output enable, facilitates true bi-directional I/O design.
21. Synchronous Preset and Asynchronous Reset
One synchronous preset line is provided for all 20 registers in the ATF750LVC. The appropri-
ate input signals to cause the internal clocks to go to a high state must be received during a
synchronous preset. Appropriate setup and hold times must be met, as shown in the switching
waveform diagram.
An individual asynchronous reset line is provided for each of the 20 flip-flops. Both master and
slave halves of the flip-flops are reset when the input signals received force the internal resets
high.
22. Security Fuse Usage
A single fuse is provided to prevent unauthorized copying of the ATF750LVC fuse patterns.
Once the security fuse is programmed, all fuses will appear programmed during verify.
The security fuse should be programmed last, as its effect is immediate.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ATF750LVC-15PU | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 750 GATE LOW POWER - 15NS RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ATF750LVC-15SC | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 750 GATE LOW POWER - 15NS 24 RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ATF750LVC-15SI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 750 GATE LOW POWER - 15NS 24 RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ATF750LVC-15SU | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 750 GATE LOW POWER - 15NS RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ATF750LVC-15X(1) | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:High-speed Complex Programmable Logic Device |
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